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US 6,212,122 B1Granted
Dual port memory operation method with synchronized read and write pointers
AssigneeNational Semiconductor Corporation
InventorSheung-Fan Wen
Life of this patent
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Abstract
A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.
Claims5
A method for operating a dual port memory suitable for transferring an address pointer across clock domains comprising the steps of:
- generating a first clock signal having a first frequency wherein circuit elements operating based upon the first clock signal operate in a first clock domain;
- generating a second clock signal having a second frequency wherein circuit elements operating based upon the second clock signal operate in a second clock domain, and wherein the first and second clock signals are asynchronous;
- generating a first synchronization signal, wherein the first synchronization signal includes a first token and a second token;
- receiving a first address pointer based upon the first token of the first synchronization signal;
- generating a second synchronization signal having a first token, wherein the first token of the first synchronization signal is passed from the first clock domain to the second clock domain and becomes the first token of the second synchronization signal;
- and
- transferring a first address pointer from the first clock domain to the second clock domain based upon the first token of the second synchronization signal.
4 more elements
Dependencies are inferred from the claim text.