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US 6,212,118 B1Granted
Semiconductor memory
AssigneeNEC Corporation
InventorMamoru Fujita
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AssigneeNEC Corporation
InventorMamoru Fujita
Estimating the term…
A semiconductor memory includes a plurality of memory cell arrays each composed of a plurality of memory cells, each of the memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving the main word lines, power supply voltage supply line driving means connected to the sub-line lines. When a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of the sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation. When the data input/output is conducted, a replacement of a sub-word line is executed on the basis of the result of a comparison between an externally supplied row address and an internally stored row address. When the refreshing operation is conducted, the replacement of the sub-word line is executed on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation.
A semiconductor memory including a plurality of memory cell arrays each composed of a plurality of memory cells, each of said memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to said plurality of memory cells, means for driving said main word lines, power supply-voltage supply line driving means connected to said sub-word lines, wherein the number of said sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation, and wherein in the case that a redundant word line used in place of a specific sub-word line including a defective memory cell is activated, when the data input/output is conducted, a redundant sub-word line is activated on the basis of the result of a comparison between an externally supplied row address and an internally stored row address, and when the refreshing operation is conducted, said redundant sub-word line is activated on the basis of an output of an internal refresh address counter at the same time as not-redundant sub-word lines are activated.
A method for driving a semiconductor memory including a plurality of memory cell arrays each composed of a plurality of memory cells, each of said memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to said plurality of memory cells, means for driving said main word lines, power supply-voltage supply line driving means connected to said sub-lines, wherein the number of said sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation, the method including driving the semiconductor memory in such a manner that in the case that a redundant word line used in place of a specific sub-word line including a defective memory cell is activated, when the data input/output is conducted, a redundant sub-word line is activated on the basis of the result of a comparison between an externally supplied row address and an internally stored row address, and when the refreshing operation is conducted, said redundant sub-word line is activated on the basis of an output of an internal refresh address counter at the same time as not-redundant sub-word lines are activated.
Dependencies are inferred from the claim text.