Duplicate bitline self-time technique for reliable memory operation
AssigneeHitachi, Ltd.
InventorsJin-Uk Luke Shin, Kenichi Osada, Masood Khan
Life of this patent
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Abstract
A CMOS memory array, including a number of bit cells arranged in an array of N rows and M columns includes a duplicate column of bit cells that is used for self-timing. Receipt of an address will access a predetermined number of the bit cells to generate a reset signal that is used to enable sense amplifiers for sampling bit lines of the array.
Claims7
A CMOS static random access memory (ram) of the type having a plurality of bit cells arranged in a number of rows and columns forming an array, each of the bit cells storing a bit of data in true and complement form, each of the number of columns of bit cell being connected to a sense amplifier by a pair of bit lines, further comprising:
- number of sense amplifiers each respectively coupled to receive the bit lines of a corresponding one of the number of columns, each sense amplifier having an enable input for receiving an enable signal to enable sensing voltage on the bit lines;
- a duplicate column containing a predetermined number of bit cells coupled to a pair of duplicate bit lines, the number of bit cells being set to a predetermined state;
- a decoder coupled to receive an address and to the predetermined number of bit cells, the decoder operating to generate a decode enable signal to access the predetermined number of bit cells to issue therefrom a sense enable signal;
- and
- each of the sense amplifiers of each of the number of columns coupled to receive the enable signal to sample the corresponding bit lines connected thereto.
A memory circuit, including:
- an array of bit cells arranged in N rows and M columns coupled to N word lines and M bit line pairs;
- M sense amplifiers coupled to corresponding ones of the M bit lines, each of the M sense amplifiers having a sense input for receiving an enable signal;
- a duplicate column containing a number of duplicate bit cells;
- and
- a control circuit coupled to receive address signals for generating therefrom a decode enable signal that is coupled to a duplicate bit line to access the number of duplicate bit cells, generating therefrom the enable signal.
A method of generating a sense enable signal for application to sense amplifiers of a memory array of a type having N rows and M columns of bit cells, the method including the steps of
- providing a duplicate column of R bit cells, where R is an integer less than or equal to M;
- coupling the outputs of the a number of the R bit cells together;
- using a produced signal to access the number of the R bit cells to generate an enable signal for application to the sense amplifiers.
Dependencies are inferred from the claim text.