Methods of identifying defects in an array of memory cells and related integrated circuitry

Abstract

Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0n, D0n*, where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells. A defect-identifying condition is imposed on the array by placing the cell plate into a first test state, and, using the write circuitry, placing both of the input lines into a common second test state which is different from the first test state.

Dependencies are inferred from the claim text.