Semiconductor memory device input circuit
AssigneeNEC Corporation
InventorKazunori Maeda
Life of this patent
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Abstract
A double-data rate (DDR) memory device is disclosed that can be configured for testing on an ordinary memory tester. The DDR memory may include a DDR input circuit (102), a single data rate input circuit (104), a word line control circuit (106), a bit line control circuit (108), and a memory cell array (110). Normal write operations may be performed by selecting the DDR input circuit (102). Test write operations may be performed by selecting the SDR input circuit (104). Such an arrangement can enable a DDR memory device to be tested in an ordinary SDR memory tester.
Claims20
A semiconductor memory device, comprising:
- a first terminal that can receive sequential data values;
- a first mode input circuit connected to the first terminal that includes at least one first latch circuit and at least one second latch circuit that alternately latch the sequential data values, the alternately latched data values propagating through the at least one first latch circuit and the at least one second latch circuit in response to a first, second and third clock signal;
- a test mode input circuit connected to the first terminal that includes at least one third latch circuit that latches data according to the first clock signal;
- wherein
- data can be written to memory cells through the first mode input circuit in a first mode and through the test mode input circuit in a test mode.
A semiconductor device, comprising:
- a data input terminal;
- a test input circuit coupled to the data input terminal that latches a first number of sequential data values within one cycle of a first clock signal in a test mode;
- and
- a first input circuit coupled the data input terminal that latches a second number of sequential data values within one cycle of the first clock signal in a first mode, the second number being greater than the first number.
A semiconductor device, comprising:
- a test input circuit that latches data from a data input terminal at a first rate in response to a first clock signal in a test mode;
- and
- a first input circuit that latches data from the data input terminal at a second rate that is faster than the first rate in response to a third clock signal, the first input circuit being disabled in the test mode.
Dependencies are inferred from the claim text.