Method to verify the integrity of the decoding circuits of a memory
AssigneeSTMicroelectronics S.r.l.
InventorsDavid Naura, Frederic Moncada
Life of this patent
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Abstract
A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.
Claims34
A method for verifying integrity of decoding circuits of a memory comprising a matrix of storage cells defined by N rows and M columns of L-bit words, the method comprising the steps of:
- writing a first word in the L-bit words for the storage cells, the matrix having N*M*L storage cells accessible by N*M addresses per L-bit word, with N, M and L being positive integers greater than 1;
- writing at least N or M second words in the matrix of storage cells so that each row and each column has at least one stored second word, the second words being different from the first word;
- and
- reading all the first and second words stored in the matrix of storage cells.
A method for verifying integrity of decoding circuits of a memory comprising a matrix of storage cells, the method comprising the steps of:
- writing a first word in the storage cells;
- writing a plurality of second words in the matrix of storage cells so that each row and each column has at least one stored second word, the second words being different from the first word;
- and
- reading all the first and second words stored in the matrix of storage cells.
A method for verifying integrity of decoding circuits of a memory comprising a matrix of storage cells defined by N rows and M columns of L-bit words, the method comprising the steps of:
- writing a first word in the L-bit words for the storage cells, the matrix having N*M*L storage cells accessible by N*M addresses per L-bit word, with N, M and L being positive integers greater than 1;
- writing N second words if N is greater than M or writing M second words if M is greater than N in the matrix of storage cells so that each row and each column has at least one stored second word, the matrix of storage cells defining at least one storage block having as many word lines as word columns such that the N or M second words are written to diagonal storage cells in the at least one storage block, the second words being different from the first word;
- and
- reading all the first and second words stored in the matrix of storage cells.
A memory device comprising:
- a matrix of storage cells defined by N rows and M columns of L-bit words;
- a decoder circuit for selecting storage cells in said matrix;
- and
- a test circuit for verifying integrity of said decoder circuit by the steps of:
- writing a first word in the storage cells,
- writing a plurality of second words in said matrix of storage cells so that each row and each column has at least one stored second word, the second words being different from the first word, and
- reading all the first and second words stored in said matrix of storage cells.
Dependencies are inferred from the claim text.