Distributed voltage charge circuits to reduce sensing time in a memory device
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsTakao Akaogi, Lee Edward Cleveland
Life of this patent
Estimating the term…
Abstract
A memory device (100) includes a core cell array (102), a sense amplifier circuit (110), data lines (120), each having a length. The memory device further includes bit lines (118) extending from the core cell array and a selection circuit (106) configured to selectively couple a bit line to a data line in response to an input address. Bias circuits (130) are distributed along the length of the data lines and are configured to apply an initial voltage to the data line, reducing the read access time of the memory device. The bias circuits 130 may be positioned to accommodate varying lengths of the data lines and varying capacitance of the data lines.
Claims20
A memory device comprising:
- a core cell array;
- a sense amplifier circuit;
- data lines, each data line having a length;
- bit lines extending from the core cell array;
- a selection circuit configured to selectively couple a bit line to a data line in response to an input address;
- and
- bias circuits distributed along the length of the data lines and configured to apply an initial voltage to the data line, the bias circuits positioned according to at least one of topological layout of the memory device and capacitive loading on the data lines.
A memory device comprising:
- a core cell array including a plurality of bit lines;
- a selection circuit coupled to the core cell array for selectively coupling one or more bit lines to data lines in response to an input address;
- sense amplifiers coupled to the data lines and configured to sense data in the core cell array at locations associated with the input address when the selection circuit couples the one or more bit lines to the data lines;
- and
- one or more bias circuits coupled to plural locations of associated data lines for charging a voltage of the associated data lines to an initial level, the number of the one or more bias circuits being selected according to at least one of topological layout of the memory device and capacitive loading on the data lines.
A method for reducing read access time in a memory device, the method comprising the steps of:
- charging data lines of the memory device to an initial voltage at a plurality of locations along lengths of the data lines, the plurality of locations chosen according to at least one of topological layout of the memory device and capacitive loading on the data lines;
- detecting a voltage variation from the initial voltage on one data line;
- sensing the voltage variation to read a state of an addressed core cell of the memory device.
Dependencies are inferred from the claim text.