Back to results
US 6,212,107 B1Granted
Charge pump circuit and a step-up circuit provided with same
AssigneeNEC Corporation
InventorShyuichi Tsukada
Life of this patent
Estimating the term…
Abstract
The invention relates to a charge pump circuit that carries out multiple-voltage rectification using a first clock, a second clock, and a third clock and outputs a stepped-up voltage, the charge pump circuit having a construction that includes a leak current suppressing circuit that outputs a third clock at amplitude of the stepped-up voltage during normal operation and outputs a third clock at amplitude of an external power supply voltage or less during a burn-in test, whereby a leak current does not flow at the junction portions of transistors and transistors do not break down due to overvoltage even during a burn-in test.
Claims20
A charge pump circuit for performing multiple-voltage rectification by a first clock, a second clock, and a third clock, and outputting a stepped-up voltage, comprising:
- a first step-up capacitor for receiving said first clock composed of a prescribed cycle;
- a second step-up capacitor for receiving said second clock that becomes high level during the interval that said first clock is low level;
- a third step-up capacitor for receiving said third clock that becomes high level during the interval that said first clock is high level;
- a first transistor that receives the output clock of said first step-up capacitor, that turns ON/OFF in accordance with the output clock of said third step-up capacitor, and that is provided for outputting said stepped-up voltage that is higher than an external power supply voltage supplied from outside;
- a second transistor that turns ON/OFF in accordance with the output clock of said second step-up capacitor and that is provided for biasing the output voltage of said first step-up capacitor by the external power supply voltage;
- a third transistor that turns ON/OFF in accordance with the output clock of said second step-up capacitor and that is provided for biasing the output voltage of said third step-up capacitor by the external power supply voltage;
- and
- a fourth transistor that turns ON/OFF in accordance with the output clock of said third step-up capacitor and that is provided for biasing the output voltage of said second step-up capacitor by the external power supply voltage;
- said charge pump circuit further including:
- a leak current suppressing circuit that outputs said third clock at amplitude of said stepped-up voltage during normal operation and outputs said third clock at amplitude of said external power supply voltage during a burn-in test.
7 more elements
A step-up circuit comprising:
- a charge pump circuit according to claims ;
- a clock generating circuit for generating said first clock, said second clock, and said third clock, and for outputting each of said clocks to said charge pump circuit;
- a decision circuit for comparing a prescribed set voltage that is generated based on a reference voltage and said stepped-up voltage, transmitting as a status signal a signal for halting the oscillation of said clock generating circuit if said stepped-up voltage is greater than said set voltage, and transmitting as a status signal a signal for continuing the oscillation of said clock generating circuit if said stepped-up voltage is equal to or lower than said set voltage;
- and
- a voltage detecting circuit for detecting the level of said external power supply voltage, and outputting a burn-in mode signal instructing switching to a mode corresponding to a burn-in test when said external power supply voltage is equal to or higher than a prescribed operating voltage, or when a signal instructing the execution of a burn-in test is received.
2 more elements
A charge pump circuit for performing multiple-voltage rectification in accordance with a first clock, a second clock, and a third clock and outputting a stepped-up voltage, comprising:
- a first step-up capacitor for receiving said first clock composed of a prescribed cycle;
- a second step-up capacitor for receiving said second clock that becomes high level in the interval that said first clock is low level;
- a third step-up capacitor for receiving said third clock that becomes high level in the interval that said first clock is high level;
- a first transistor that receives the output clock of said first step-up capacitor, that turns ON/OFF in accordance with the output clock of said third step-up capacitor, and that is provided for outputting said stepped-up voltage that is higher than an external power supply voltage that is supplied from outside;
- a second transistor that turns ON/OFF in accordance with the output clock of said second step-up capacitor and that is provided for biasing the output voltage of said first step-up capacitor by the external power supply voltage;
- a third transistor that turns ON/OFF in accordance with the output clock of said second step-up capacitor and that is provided for biasing the output voltage of said third step-up capacitor by the external power supply voltage;
- and
- a fourth transistor that turns ON/OFF in accordance with the output clock of said third step-up capacitor and that is provided for biasing the output voltage of said second step-up capacitor by the external power supply voltage;
- said charge pump circuit further including:
- a first leak current suppressing circuit for outputting said first clock at amplitude of said external power supply voltage during normal operation, and for outputting said first clock at a prescribed amplitude that is lower than said external power supply voltage during a burn-in test;
- a second leak current suppressing circuit for outputting said second clock at amplitude of said external power supply voltage during normal operation, and for outputting said second clock at a prescribed amplitude that is lower than said external power supply voltage during a burn-in test;
- and
- a third leak current suppressing circuit for outputting said third clock at amplitude of said stepped-up voltage during normal operation, and for outputting said third clock at a prescribed amplitude that is lower than said stepped-up voltage during a burn-in test.
10 more elements
A step-up circuit comprising:
- a step-up section for outputting a stepped-up voltage in which the power supply voltage has been stepped up;
- a step-up control unit for outputting to said step-up section switching signals of a higher voltage than said stepped-up voltage;
- and
- a leak current suppressing means for suppressing the maximum voltage occurring inside said step-up control unit to less than the leak initiation voltage of transistor that make up said step-up control unit.
1 more element
A semiconductor memory device comprising:
- a step-up section for outputting a stepped-up voltage in which a power supply voltage is stepped up;
- a step-up control unit for outputting to said step-up section switching signals of a higher voltage than said stepped-up voltage;
- a leak current suppressing means for suppressing the maximum voltage occurring in said step-up control unit to less than the leak-initiating voltage of first transistors that make up said step-up control unit;
- and
- second transistors that make up a memory unit;
- wherein said first transistors and said second transistors are formed in the same semiconductor substrate or well.
3 more elements
A semiconductor memory device comprising:
- a step-up section for outputting a stepped-up voltage in which a power supply voltage is stepped up;
- a step-up control unit for outputting to said step-up section switching signals of a higher voltage than said stepped-up voltage;
- a leak current suppressing means for suppressing the maximum voltage occurring in said step-up control unit to less than a leak-initiating voltage of first transistors that make up said step-up control unit;
- and
- second transistors that make up a memory unit;
- wherein said first transistors are formed in a first well region;
- said second transistors are formed in a second well region;
- and
- said first well region and said second well region are connected to the same well potential biasing means.
6 more elements
Dependencies are inferred from the claim text.