Method for operating flash memory
AssigneeXilinx, Inc.
InventorsMichael G. Ahrens, Anders T. Dejenfelt, Qi Lin, Robert A. Olah
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Abstract
A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.
Claims13
A method of operating an array of one or more non-volatile memory transistors, each non-volatile memory transistor including a floating gate, a source, a drain, and a control gate, the method comprising:
- an erase operation wherein electrons are inserted into the floating gate of each non-volatile memory transistor in the array by applying a first voltage across the control gate and the source of each non-volatile memory transistor for a first time period;
- a program operation wherein electrons are removed from the floating gate of each non-volatile memory transistor in a first set of the array, thereby lowering the threshold voltage of each non-volatile memory transistor in the first set;
- and
- a soft erase operation performed after the program operation wherein electrons are inserted into the floating gate of each non-volatile memory transistor in the array by applying a second voltage across the control gate and the source of each non-volatile memory transistor for a second time period while leaving the drain of each non-volatile memory transistor floating, wherein the second voltage is less than the first voltage and the second time period is less than the first time period.
Dependencies are inferred from the claim text.