High-density nor-type flash memory device and a program method thereof

A NOR-type flash memory device comprising:

• an array of a plurality of memory cells arranged in rows and columns;
• a row selecting circuit for selecting one of the rows;
• a column selecting circuit for selecting one or more of a group of the columns;
• a pump circuit for generating a drain voltage to be supplied to the selected group of columns during a program operation;
• a program period control circuit for generating first and second program period signals indicating a program period of memory cells assigned by the selected row and column group;
• a select circuit for generating select signals assigning the selected column group respectively in response to the first and second program period signals and data bits to be programmed to the assigned memory cells;
• and
• a write driver circuit for driving the selected column group with the drain voltage from the pump circuit in response to the select signals,
• wherein the program period control circuit generates the first program period signals each corresponding to the assigned memory cells so that the assigned memory cells are sequentially programmed up to a predetermined threshold voltage which is less than a target threshold voltage;
• and wherein the program period control circuit generates the second program period signal so that the assigned memory cells are simultaneously programmed up to the target threshold voltage from the predetermined threshold voltage.

A NOR-type flash memory device comprising:

• an array of a plurality of memory cells arranged in rows and columns;
• a row selecting circuit for selecting one of the rows;
• a column selecting circuit for selecting ones of the columns into a column group;
• a pump circuit for generating a drain voltage to be supplied to the column group during a program operation;
• a program period control circuit for generating first and second program period signals indicating a program period of memory cells assigned by the selected row and column group;
• a select circuit for generating select signals assigning the column group respectively in response to the first and second program period signals and data bits to be programmed to the assigned memory cells;
• and
• a write driver circuit for driving the column group with the drain voltage from the pump circuit in response to the selected signals,
• wherein the program period control circuit generates the first program period signals each corresponding to the assigned memory cells so that the assigned memory cells are sequentially programmed up to a predetermined threshold voltage which is less than a target threshold voltage;
• and wherein the program period control circuit generates the second program period signals so that plural groups of the assigned memory cells each having the predetermined threshold voltage are sequentially programmed, the assigned memory cells of each group being simultaneously programmed.