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US 6,212,099 B1Granted
Preventing data corruption in a memory device using a modified memory cell conditioning methodology
AssigneeIntel Corporation
InventorsSuibin Zhang, Ravi Annavajjhala, Robert L. Baltar, Dow-Ping D. Wong, Marc E. Landgraf
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Abstract
An embodiment of the invention is directed to a method of operating a flash memory, which includes discharging at least one local wordline of an unselected block of flash memory cells during an interval in which a selected set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the unselected block.
Claims22
A method of operating a flash memory, comprising:
- discharging at least one local wordline that is coupled to a first set of flash memory cells, during an interval in which a second set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the first set;
- and
- erasing the second set after the interval in which the second set is conditioned, wherein the conditioning avoids overerasure of the second set.
A storage device comprising:
- first set of flash memory cells having a plurality of groups of first cells;
- plurality of first local wordlines each coupled to a respective one of the plurality of groups of first cells;
- second set of flash memory cells having a plurality of groups of second cells;
- plurality of second local wordlines each coupled to a respective one of the plurality of groups of second cells;
- and
- controller being configured to cause the first local wordlines to discharge during an interval in which the second set of flash memory cells are conditioned, and then the second set of cells to be erased after being conditioned, and wherein the second set of cells are conditioned to avoid subsequent overerasure.
3 more elements
An electronic system comprising:
- bus;
- processor coupled to the bus;
- and
- flash memory device coupled to the bus for containing instructions to be executed by the processor, the flash memory device comprising a first set of flash memory cells having a plurality of groups of first cells, a plurality of first local wordlines each coupled to a respective one of the plurality of groups of first cells, a second set of flash memory cells having a plurality of groups of second cells, a plurality of second local wordlines each coupled to a respective one of the plurality of groups of second cells, and a controller being configured to cause the first local wordlines to discharge during an interval in which the second set of flash memory cells are conditioned, and then the second set of cells to be erased after being conditioned, and wherein the second set of cells are conditioned to avoid subsequent overerasure.
1 more element
Dependencies are inferred from the claim text.