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US 6,212,095 B1Granted
Integrated circuit charge coupling circuit
AssigneeMicron Technology, Inc.
InventorChristophe J. Chevallier
Life of this patent
Estimating the term…
Abstract
A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive coupling circuit in one embodiment is included in a memory device for coupling a charge pump to a memory array word line. The resistive coupling circuit can be either a single resistor, a plurality of resistors, or a coupling circuit which has substantially resistive characteristics.
Claims25
A method of operating a circuit comprising:
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a load circuit.
1 more element
A method of operating a circuit comprising:
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a load circuit having a capacitance.
1 more element
A method of operating a memory device comprising:
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit in a memory device;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a load circuit in the memory device.
1 more element
A method of operating a memory device comprising:
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit in a memory device;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a decode circuit connected to a word line in the memory device.
1 more element
A method of operating a system comprising:
- exchanging control signals between a microprocessor and an integrated circuit;
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit in the integrated circuit;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a load circuit in the integrated circuit.
2 more elements
A method of operating a memory device comprising:
- exchanging control signals between a microprocessor and a memory device;
- generating an elevated voltage on a plate of an output capacitor in a charge pump circuit in the memory device;
- modifying the elevated voltage in a resistor circuit having no diodes or transistors to generate a modified voltage, the resistor circuit being connected to the plate of the output capacitor;
- and
- connecting the modified voltage to a decode circuit connected to a word line in the memory device.
2 more elements
A circuit comprising:
- a charge pump circuit to generate an elevated voltage on a plate of an output capacitor;
- a load circuit;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the load circuit to couple the elevated voltage to the load circuit.
1 more element
A circuit comprising:
- a charge pump circuit to generate an elevated voltage on a plate of an output capacitor;
- a load circuit having a capacitance;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the load circuit to couple the elevated voltage to the load circuit.
1 more element
A memory device comprising:
- a charge pump circuit in a memory device to generate an elevated voltage on a plate of an output capacitor;
- a load circuit in the memory device;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the load circuit to couple the elevated voltage to the load circuit.
1 more element
A memory device comprising:
- a charge pump circuit to generate an elevated voltage on a plate of an output capacitor in a memory device;
- a plurality of memory cells coupled to a word line and a decode circuit in the memory device;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the decode circuit and the word line to couple the elevated voltage to the decode circuit and the word line.
1 more element
A system comprising:
- a microprocessor;
- and
- an integrated circuit coupled to the microprocessor, the integrated circuit comprising:
- a charge pump circuit to generate an elevated voltage on a plate of an output capacitor;
- a load circuit;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the load circuit to couple the elevated voltage to the load circuit.
4 more elements
A system comprising:
- a microprocessor;
- and
- a memory device coupled to the microprocessor, the memory device comprising:
- a charge pump circuit to generate an elevated voltage on a plate of an output capacitor;
- a plurality of memory cells coupled to a word line and a decode circuit;
- and
- a resistor circuit having no diodes or transistors connected between the plate of the output capacitor and the decode circuit and the word line to couple the elevated voltage to the decode circuit and the word line.
4 more elements
A circuit comprising:
- a charge pump circuit having a plurality of pump capacitors to produce an elevated voltage;
- a load circuit having a capacitance;
- and
- means for coupling one of the pump capacitors having the elevated voltage to the load circuit with a resistance and having no diodes or transistors.
1 more element
Dependencies are inferred from the claim text.