US 6,212,092 B1 · Semiconductor integrated circuit

Abstract

The semiconductor integrated circuit comprises a memory cell, a sense amplifier, input/output controlling circuit, a switch circuit which connects the sense amplifier and the input/output circuit, a reference timing signal generator, a timing controlling circuit having a delay element, and a switch controlling circuit which controls the switch circuit. The reference timing signal generator generates a reference timing signal necessary for read/write operations. The timing controlling circuit receives the reference timing signal and generates, by using the delay element thereof, at least one of either a read controlling signal or a write controlling signal whose timing shifts from the timing of the switch controlling signal by a predetermined amount of time. Therefore, the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal can easily be set to a predetermined value. The timing deviation is not easily affected by fluctuations occurring in a manufacturing process, an operation voltage, or ambient temperature. Therefore, it is possible to carry out the timing design to minimize the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal. As a result, a high-speed operation can be performed. When the high-speed operation is not pursued, it is possible to increase timing margins of other circuits so that the yield improves.

Claims14

Dependent claims

A semiconductor integrated circuit comprising:

a memory cell;
a sense amplifier for amplifying data read from and written to said memory cell;
an input/output controlling circuit comprising at least one of either a read controlling circuit receiving said data amplified by said sense amplifier in a read operation or a write controlling circuit for outputting said data to said sense amplifier in a write operation;
a switching circuit for carrying out on/off control of a transmission path of said data between said sense amplifier and said input/output controlling circuit;
a reference timing signal generator for generating a reference timing signal used in said read operation and said write operation;
a timing controlling circuit for receiving said reference timing signal and for generating at least one of either a read controlling signal or a write controlling signal for controlling said input/output controlling circuit;
and
a switch controlling circuit for receiving said reference timing signal and for generating a switch controlling signal for the on/off control of said switching circuit, wherein
said timing controlling circuit comprises a delay element identical or equivalent to a delay element existing in said switch controlling circuit.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims14