Semiconductor memory device having a shielding line

Abstract

A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed between the column selection line and a data bus line adjacent to the column selection line. The shielding line electrically shields the data bus line from the column selection line. Therefore, the semiconductor memory device having the high speed data bus can be achieved because the coupling capacitance between the column selection line and the data bus line is reduced.

Dependencies are inferred from the claim text.