Efficient error correction in pipelined analog-to-digital converters

A circuit for correcting errors in N digital words generated by N+1 pipelined analog-to-digital converters, the circuit comprising:

• N groups of pipeline registers, each group coupled to a respective one of the first N of the pipelined analog-to-digital converters, the N groups of pipeline registers synchronizing the N digital words;
• and
• N correctors, each coupled to a respective one of the N groups of pipeline registers and correcting the respective one of the synchronized N digital words, each of the N correctors also generating an output adjustment value within an output range based on an input adjustment value within an input range by an incrementing operation or a decrementing operation, the output range and the input range being equal, the input adjustment value for the first N-1 correctors being generated by the subsequent one of the first N correctors, the input adjustment value for the Nth corrector being generated by the N+1 analog-to-digital converter.