Test circuit and method for measuring switching point voltages and integral non-linearity (INL) of analog to digital converters

A method for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the method comprising the steps of:

• comparing a digital output value from the digital output of the ADC to a predetermined digital value;
• generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• averaging voltages of the first and second logic values to provide an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• averaging the first and second logic values to generate a digital average value which is representative of the switching point voltage.

A test circuit for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the test circuit comprising:

• a digital comparator for sampling and comparing a digital output value from the digital output of the ADC to a predetermined digital value, and generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• an analog averaging circuit for averaging voltages of the first and second digital logic values, and providing an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• a digital averaging circuit for averaging the first and second digital logic values, and generating a digital average value which is representative of the switching point voltage;
• and
• a correcting circuit for calculating a difference between a first digital average value obtained at a first clock frequency and a second digital average value obtained at a second clock frequency which is higher than the first clock frequency, and correcting the first digital average value in accordance with the calculated difference.

A test circuit for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the test circuit comprising:

• a digital comparator for comparing a digital output value from the digital output of the ADC to a predetermined digital value, and generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• an analog averaging circuit for averaging voltages of the first and second digital logic values, and providing an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• a digital averaging circuit for averaging the first and second digital logic values, and generating a digital average value which is representative of the switching point voltage;
• a subtractor for subtracting the digital average value measured for a selected reference value from the selected reference value itself;
• a comparator for comparing the subtraction result with that for other selected references;
• and
• a determining circuit for determining a maximum subtraction result which differs most from zero, wherein the maximum subtraction result is representative of a maximum Integral Non-Linearity (INL) of the ADC.

A test circuit for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the test circuit comprising:

• a digital comparator for comparing a digital output value from the digital output of the ADC to a predetermined digital value, and generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• an analog averaging circuit for averaging voltages of the first and second digital logic values, and providing an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• a digital averaging circuit for averaging the first and second digital logic values, and generating a digital average value which is representative of the switching point voltage;
• a subtractor for subtracting a first digital average value measured for a first predetermined digital value from a second digital average value measure for a second predetermined digital value which differs from the first predetermined value by one least significant bit (LSB);
• and
• a determining circuit for determining a maximum subtraction result which differs most from an ideal subtraction result, wherein the maximum subtraction result is representative of a maximum Differential Non-Linearity (DNL) of the ADC.

A method for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the method comprising of steps of:

• comparing a digital output value from the digital output of the ADC to a predetermined digital value;
• generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• averaging voltages of the first and second logic values to provide an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• averaging the first and second logic values to generate a digital average value which is representative of the switching point voltage;
• calculating a difference between a first digital average value obtained at a first clock frequency and a second digital average value obtained at a second clock frequency which is higher than the first clock frequency;
• and
• correcting the first digital average value in accordance with the difference.

A method for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the method comprising the steps of:

• comparing a digital output value from the digital output of the ADC to a predetermined digital value;
• generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• averaging voltages of the first and second logic values to provide an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• averaging the first and second logic values to generate a digital average value which is representative of the switching point voltage;
• subtracting the digital average value measured for a selected reference value from the selected reference value itself;
• comparing the subtraction result with that for other selected references;
• and
• determining a maximum subtraction result which differs most from zero, wherein the maximum subtraction result is representative of a maximum Integral Non-Linearity (INL) of the ADC.

A method for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output, the method comprising the steps of

• comparing a digital output value from the digital output of the ADC to a predetermined digital value;
• generating a first logic value when the digital output value is less than a predetermined value, and a second logic value when the digital output value is equal to or greater than the predetermined value;
• averaging voltages of the first and second logic values to provide an analog average value to the analog input of the ADC such that the analog input of the ADC receives no external analog input signal during the measurement;
• averaging the first and second logic values to generate a digital average value which is representative of the switching point voltage;
• subtracting a first digital average value measured for a first predetermined digital value from a second digital average value measured for a second predetermined digital value which differs from the first predetermined value by one least significant bit (LSB);
• and
• determining a maximum subtraction result which differs most from an ideal subtraction result, wherein the maximum subtraction result is representative of a maximum Differential Non-Linearity (DNL) of the ADC.