Switching a clocked device from an initial frequency to a target frequency
AssigneeIntel Corporation
InventorsXia Dai, Keng Wong
Life of this patent
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Abstract
Switching a clocked device from an initial frequency to a target frequency includes locking a first phase locked loop (PLL) to the target frequency while a second PLL is driving a clock distribution network at the initial frequency. The first PLL is then substituted for the second PLL on the clock distribution network.
Claims24
A method of switching a clocked device from an initial frequency to a target frequency, comprising:
- locking a first phase locked loop (PLL) to the target frequency while a second PLL is driving a clock distribution network at the initial frequency;
- and
- substituting the first PLL for the second PLL on the clock distribution network.
A method of switching a frequency of a clock distribution network in a processor, comprising:
- tuning a delay locked loop (DLLP) to a delay of the clock distribution network;
- setting the DLLP to a target frequency;
- switching an input and an output of a first phase locked loop (PLL) into the DLLP so that the first PLL is at the target frequency;
- locking the first PLL in phase with an external clocking signal while a second PLL is driving the clock distribution network;
- substituting an output of the first PLL for an output of the second PLL on the clock distribution network;
- setting a frequency of the clock distribution network to the target frequency;
- and
- switching a feedback from the clock distribution network from an input of the second PLL into an input of the first PLL.
An apparatus which switches a clocked device from an initial frequency to a target frequency, comprising:
- a first phase locked loop (PLL) which locks at the target frequency;
- a second PLL which drives a clock distribution network at the initial frequency;
- and
- switches which substitute the first PLL for the second PLL on the clock distribution network.
An apparatus for switching a frequency of a clock distribution network in a processor, comprising:
- a delay locked loop (DLLP) tuned to a delay of the clock distribution network;
- a frequency divider in the DLLP set in accordance with a target frequency;
- circuitry which locks a first phase locked loop (PLL) to the target frequency via the DLLP while a second PLL is driving the clock distribution network;
- switches which substitute an output of the first PLL for an output of the second PLL on the clock distribution network, and which switch a feedback from the clock distribution network from an input of the second PLL into an input of the first PLL;
- and
- a frequency divider in the clock distribution network that is set in accordance with the target frequency based on a time of operation of the switches.
A method of switching a clock distribution network from an initial frequency to a target frequency, comprising:
- simulating the clock distribution network;
- locking a first phased locked loop (PLL) to a target frequency via the simulated clock distribution network while a second PLL is driving the clock distribution network at the initial frequency;
- and
- replacing the second PLL with the first PLL on the clock distribution network.
Dependencies are inferred from the claim text.