Microprocessor controlled frequency lock loop for use with an external periodic signal
AssigneeCypress Semiconductor Corporation
InventorsWarren S. Synder, Fred Jaccard
Life of this patent
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Abstract
A circuit comprising an oscillator configured to provide a first output signal in response to one or more input signals. A divider circuit may be configured to receive the first output signal of the oscillator circuit and to present a signal having a second frequency at a second output. A frequency comparator circuit may receive the second output signal and an external signal having a third frequency and may present a third output signal representing control information. A processor circuit may be coupled to the oscillator circuit, the divider circuit and the comparator circuit. The processor circuit may control the frequency of oscillation of the first output.
Claims19
A circuit comprising:
- a digitally controlled oscillator circuit configured to provide a first output signal having a first frequency of oscillation in response to one or more input signals;
- a comparator circuit configured (i) to receive said first output signal, (ii) to receive an external signal having a second frequency of oscillation and (iii) to present a second output signal having a first logic state when a difference in frequency between said first output and said external signal is greater than a predetermined value and a second logic state when said difference is less than said predetermined value;
- and
- a processor circuit configured to receive said second output signal from said comparator circuit, said processor configured to (i) control the first frequency of oscillation by adjusting said one or more input signals, (ii) adjust the first frequency of oscillation of said first output signal by performing an interrupt routine executed by said processor when said second output signal is at said second logic state and (iii) not adjust the first frequency of oscillation of said first output signal when said second output signal is at said first logic state.
A circuit comprising:
- a digitally controlled oscillator for generating a first output signal having a first frequency of oscillation in response to one or more input signals;
- means for generating a second output signal having a first logic state when a difference in frequency between said first output and an external signal having a second frequency is greater than a predetermined value and a second logic state when said difference is less than said predetermined value;
- means for receiving said second output signal;
- and
- means for (i) controlling the first frequency of oscillation by adjusting said one or more input signals, (ii) changing said one or more input signals by performinq an interrupt routine executed by said generating means when said second output signal is at said second logic state and (ii) not adjust the frequency of oscillation of said first output signal when said second output is at said first logic state.
A method for synchronizing an output signal with an external signal, comprising:
- digitally generating said output signal in response to one or more input signals;
- comparing said output signal with said external signal to generate an interrupt signal when a difference between said one or more input signals and said external reference signal is greater than a predetermined value;
- receiving said interrupt signal;
- and
- adjusting said one or more input signals by performing an interrupt routine executed by said processor when said interrupt signal is at a first logic state and not adjusting said one or more input signals when said interrupt signal is not at said first logic state.
Dependencies are inferred from the claim text.