US 6,211,722 B1 · Low voltage high speed multiplexer and latch

Abstract

A high speed and low power digital circuit for producing an output responsive to a plurality of input data signals, such as a multiplexer or a latch includes one or more data switching elements. Each of the switching elements is a differential transistor pair having one transistor driven by a control signal and the other transistor driven by a data signal. The signal levels for the data and control signals are interleaved so that each control signal turns on and off the effect of the data signal on the current flow in the switching element. The circuit structure avoids emitter coupling more than two transistors at any point in order to reduce the capacitance at critical nodes and consequently increase switching speed. By providing two switching elements with data transistors connected to a common pull-down resistor, two data signals, and a complementary pair of control signals, a multiplexing function can be performed. A second pair of similarly connected switching elements can be provided and supplied with inverted input data signals to provide complementary data output signals. The output signals can be cross-coupled to one complementary pair of data inputs to form a high speed, low voltage latch.

Claims10

Dependent claims

A digital circuit for producing an output responsive to a plurality of input data signals in accordance with respective data control signals and connected between a first supply voltage node (“VCC”) and a second supply voltage node (“VEE”), the circuit comprising:

a resistance connected between VCC and a data node;
and
at least one data switching element connected to VCC, to VEE, and to said data node, the switching element for receiving a respective data signal switchable between a first high voltage level (“DATAHIGH”) and a first low voltage level (“DATALOW”) and a respective control signal switchable between a second high voltage level (“CKHIGH”) and a second low voltage level (“CKLOW”), where CKHIGH>DATAHIGH>CKLOW>DATALOW;
each of said at least one data switching elements comprising:
a current sink connected to VEE;
a first transistor connected between VCC and the current sink and controlled by the respective control signal;
and
a second transistor connected between the data node and the current sink and controlled by the respective data signal.

5 more elements

A digital circuit for producing an output responsive to a plurality of input data signals in accordance with respective data control signals and connected between a first supply voltage (“VCC”) and a second supply voltage (“VEE”), the circuit comprising:

a first differential pair comprising a first selection transistor, a first data transistor, and a first current sink;
the first selection transistor being connected between VCC and the first current sink and being controlled by a first data control signal switchable between a first high voltage level (“CKHIGH”) and a first low voltage level (“CKLOW”);
the first data transistor connected between a primary data node and the first current sink and being controlled by a first input data signal switchable between a second high voltage level (“DATAHIGH”) and a second low voltage level (“DATALOW”);
a first resistance connected between VCC and the primary data node;
a second differential pair comprising a second selection transistor, a second data transistor, and a second current sink;
the second selection transistor being connected between VCC and the second current sink and being controlled by a second data control signal switchable between CKHIGH and CKLOW;
the second data transistor connected between the primary data node and the second current sink and being controlled by a second input data signal having a voltage switchable between DATAHIGH and DATALOW;
the voltage at said primary data node indicating one of the data value of either of said first or second input data signals when CKHIGH>DATAHIGH>CKLOW>DATALOW and said second data control signal is the logical inverse of said first data control signal.

5 more elements

Dependencies are inferred from the claim text.

Low voltage high speed multiplexer and latch

Life of this patent

Low voltage high speed multiplexer and latch

Life of this patent

Abstract

Claims10