Multiple differential pair transistor architecture having transconductance proportional to bias current for any transistor technology

A method of linearly varying the transconductance, gm, of a multiple differential pair circuit with respect to an bias current, I0, said method comprising the steps of:

• coupling a plurality of differential transistor pair circuits in parallel, wherein said differential transistor pair circuits are comprised of transistors operating in a non-exponential voltage-current (V-I) region;
• and
• varying the transconductance, gm, of said multiple differential pair circuit by applying said bias current, I0, to each of said differential pairs.

A gain control circuit comprised of:

• at least one multiple differential pair circuit having a transconductance, gm, that varies linearly with a bias current, I0, said circuit comprising a plurality of differential transistor pair circuits coupled in parallel, wherein said differential transistor pair circuits are comprised of transistors operating in a non-exponential voltage-current (V-I) region.

An analog multiplier comprised of:

• at least one multiple differential pair circuit having a transconductance, gm, that varies linearly with a bias current, I0, said circuit comprising a plurality of differential transistor pair circuits coupled in parallel, wherein said differential transistor pair circuits are comprised of transistors operating in a non-exponential voltage-current (V-I) region.

A filter comprised of:

• at least one multiple differential pair circuit having a transconductance, gm, that varies linearly with a bias current, I0, said circuit comprising a plurality of differential transistor pair circuits coupled in parallel, wherein said differential transistor pair circuits are comprised of transistors operating in a non-exponential voltage-current (V-I) region.