Semiconductor integrated circuit incorporating therein clock supply circuit

A method for supplying to a plurality of peripheral circuits a respective plurality of frequency-divided clock signals, each of a plurality of peripheral circuits incorporated on a semiconductor integrated circuit, said method comprising the steps of:

• generating at least one frequency-divided clock signal from an external clock signal;
• supplying said at least one frequency-divided clock signal to at least one of a plurality of clock supply circuit blocks;
• generating the respective plurality of frequency-divided clock signals using the clock supply circuit blocks from said at least one frequency-divided clock;
• and
• supplying to each of the peripheral circuits all of the frequency-divided clock signals used thereby from one of said clock supply circuit blocks;
• feeding only a single frequency, different from each other, to each of said plurality of clock supply circuit blocks;
• and
• generating, in said clock supply circuit blocks said respective plurality of frequency-divided clock signals having only said single frequency and smaller frequencies.

A semiconductor integrated circuit having a plurality of peripheral circuits, each operated by a respective plurality of frequency-divided clock signals, comprising:

• a first clock supply circuit being supplied with an external clock signal and generating at least one frequency-divided signal from the external clock signal;
• a plurality second clock supply circuits, each of which is provided for at least one of said peripheral circuits to provide said at least one peripheral circuit with all of the frequency-divided clock signals that are supplied to said at least one peripheral circuit;
• and
• wherein each of said plurality of second clock supply circuits receives only a single frequency different from each other and generates said respective frequency-divided clock signals having only said single frequency and smaller frequencies.

A semiconductor integrated circuit incorporating therein at least a first and a second peripheral circuit, said first peripheral circuit operated by a first plurality of frequency-divided clock signals and said second peripheral circuit operated by a second plurality of frequency-divided clock signals, said first and second plurality of frequency-divided clock signals derived from an external clock signal comprising:

• an initial clock supply circuit block for generating an initial plurality of frequency-divided clock signals having at least a first initial frequency-divided clock signal f1 and a second, different initial frequency-divided clock signal f2,
• at least first and second clock supply circuit blocks providing output to said first and second peripheral circuits respectively,
• said first clock supply circuit block connected to said initial supply circuit block to receive only said first initial frequency-divided clock signal f1 for generating said first plurality of frequency-divided clock signals having only frequencies of f1 and smaller frequencies, and
• said second clock supply circuit block connected to said initial supply circuit block to receive only said second initial frequency-divided clock signal f2 for generating said second plurality of frequency-divided clock signals having only frequencies of f2 and smaller frequencies.

A semiconductor integrated circuit comprising:

• a first clock supply circuit for receiving a clock signal and for outputting a first clock signal and a second clock signal each having a different frequency-divide ratio;
• a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided to form a frequency-divided first clock signal, the first clock signal and the frequency-divided first clock signal being supplied to a first peripheral circuit;
• and
• a third clock supply circuit to which said second clock signal is inputted and in which said second clock signal is frequency-divided to form a frequency-divided second clock signal, the second clock signal and the frequency-divided second clock signal being supplied to a second peripheral circuit.

A semiconductor integrated circuit comprising:

• a first clock supply circuit for receiving a clock signal and for outputting a first clock signal;
• a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided to form a frequency-divided first clock signal, the first clock signal and the frequency-divided first clock signal being supplied to a first peripheral circuit;
• and
• a third clock supply circuit to which a second clock signal, which is the frequency-divided first clock signal, is inputted and in which said second clock signal is further frequency-divided to form a frequency-divided second clock signal, the second clock signal and the frequency-divided second clock signal being supplied to a second peripheral circuit.

A semiconductor integrated comprising:

• a first clock supply circuit for receiving a clock signal and for outputting a first clock signal;
• a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided and supplied to first and second peripheral circuits as frequency-divided first clock signals;
• and
• a third clock supply circuit to which a second clock signal, which is one of the frequency-divided first clock signals, is inputted and in which said second clock signal is further frequency-divided and supplied to third and fourth peripheral circuits.