Adjustable feedback for CMOS latches
AssigneeInternational Business Machines Corporation
InventorGregory John Uhlmann
Life of this patent
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Abstract
An improved latch circuit having a dynamically adjustable internal feedback level. The improved latch circuit includes a latch inverter and a feedback inverter cross-coupled with the latch inverter. A controllable supplemental feedback inverter is connected in parallel with the feedback inverter to provide a controllable level of feedback to the latch inverter. An independently selectable control signal enables or disables the controllable feedback inverter in conformity with a need for more or less feedback, such that the internal feedback level may provide optimal functionality and performance of the latch circuit.
Claims8
A latch circuit having pn adjustable internal feedback level at a feedback node, said latch circuit comprising:
- a feedforward inverter having an input connected to said feedback node;
- a steady state feedback tri-state inverter having an input connected to an output of said feedforward inverter and an output connected to said feedback node, wherein said feedback tri-state inverter receives a clock signal as its control input;
- and
- a supplementary tri-state inverter cross-coupled with said feedforward inverter such that an output of said tri-state inverter is connected to said feedback node, wherein said supplementary tri-state inverter receives a feedback control signal as its control input for enabling or disabling said supplementary tri-state inverter such that said internal feedback level at said feedback node is adjusted in accordance with both said clock signal and said feedback control signal.
A method for utilizing on integrated circuit chip having a latch circuit, said latch circuit comprising a feedforward inverter having an input connected to a feedback node, wherein said latch circuit further includes a steady state feedback tri-state inverter cross-coupled with said feed forward inverter and a supplemental tri-state inverter connected in parallel with said steady state feedback tri-state inverter, said method comprising the steps of:
- applying a clock signal representing a test mode to a control input of said supplemental tri-state inverter;
- and
- while applying said clock signal representing a test mode, performing a stress test on said latch circuit.
Dependencies are inferred from the claim text.