Activation signal generating circuit
AssigneeSTMicroelectronics S.r.l.
InventorsBernadette Laurier, Charles Odinot
Life of this patent
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Abstract
An activation signal generating circuit includes a combinational logic circuit and a switch. The combinational logic circuit receives a normal mode control signal and a test mode control signal, and the switch receives a periodic clock signal. The switch is controlled by the output of the combinational logic circuit such that an activation signal is generated from the periodic clock signal. In one preferred embodiment, the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, and a potential setting circuit imposes a specified potential at the output of the switch when the switch is open. A method of generating an activation signal is also disclosed.
Claims28
An activation signal generating circuit for generating an activation signal from a periodic clock signal the activation signal being selectively supplied as a clock signal to a circuit under test in a normal operating mode based on a normal mode control signal, and being selectively supplied as a scan test signal to clock inputs of flip-flops of the circuit under test in a test mode based on a test mode control signal said activation signal generating circuit comprising:
- a combinational logic circuit that receives the normal mode control signal and the test mode control signal;
- and
- a switch that receives the periodic clock signal, the switch being controlled by the output of the combinational logic circuit,
- wherein the combinational logic circuit controls the switch such that the switch selectively transfers the periodic clock signal as the activation signal based on the output of the combinational logic circuit, and
- the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, the two transistors being controlled by complementary signals.
The activation signal generating circuit as defined in 1,
- wherein the output of the combinational logic circuit is supplied to the control gate of one of the MOS transistors, and
- the output of the combinational logic circuit is supplied to the control gate of the other of the MOS transistors through an inverter.
An integrated circuit comprising:
- an operational circuit that operates in a normal mode and a test mode the operational circuit including a plurality of flip-flops that form at least one storage register, the flip-flops being configured as a shift register in the test mode;
- a combinational logic circuit that receives a normal mode control signal and a test mode control signal;
- and
- a switch that receives a periodic clock signal, the switch being controlled by the output of the combinational logic circuit,
- wherein the combinational logic circuit controls the switch such that the switch selectively transfers the periodic clock signal as an activation signal based on the output of the combinational logic circuit, the activation signal being selectively supplied to the flip-flops as a clock signal in the normal mode based on the normal mode control signal, and being selectively supplied to clock inputs of the flip-flops as a scan test signal in the test mode based on the test mode control signal.
The integrated circuit as defined in 13, wherein the switch is a CMOS changeover switch having two complementary MOS transistors connected in parallel, the two transistors being controlled by complementary signals.
An information handling system including at least one integrated circuit that operates in a normal mode and a test mode, said integrated circuit comprising:
- a plurality of flip-flops that form at least one storage register;
- a combinational logic circuit that receives a normal mode control signal and a test mode control signal;
- and
- a switch that receives a periodic clock signal, the switch being controlled by the output of the combinational logic circuit,
- wherein the combinational logic circuit controls the switch such that the switch selectively transfers the periodic clock signal as an activation signal based on the output of the combinational logic circuit, the activation signal being selectively supplied to the flip-flops as a clock signal in the normal mode based on the normal mode control signal and being selectively supplied to clock inputs of the flip-flops as a scan test signal in the test mode based on the test mode control signal.
The information handling system as defined in 20, wherein the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, the two transistors being controlled by complementary signals.
A method of generating an activation signal, said method comprising the steps of:
- logically combining a normal mode control signal and a test mode control signal;
- receiving a periodic clock signal;
- after logically combining the normal mode control signal and the test mode control signal selectively providing the periodic clock signal as the activation signal based on the result of the logical combination of the control signals;
- and
- supplying the activation signal to a plurality of flip-flops that form at least one storage register, the activation signal being supplied to the flip-flops as a clock signal in a normal operating mode and being supplied to the flip-flops as a scan test signal in a test mode.
The method as defined in 23, wherein the step of selectively providing the periodic clock signal includes the sub-step of selectively opening a switch based on the result of the logical combination of the control signals.
A method of generating an activation signal for an operational circuit that operates in a normal mode and a test mode, said method comprising the steps of:
- logically combining a normal mode control signal and a test mode control signal;
- receiving a periodic clock signal;
- after logically combining the normal mode control signal and the test mode control signal, selectively providing the periodic clock signal as the activation signal based on the result of the logical combination of the control signals;
- supplying the activation signal as a clock signal to a plurality of flip-flops of the operational circuit in the normal mode;
- configuring the flip-flops of the operational circuit as a shift register in the test mode;
- and
- supplying the activation signal as a scan test signal to the flip-flops of the operational circuit in the test mode.
Dependencies are inferred from the claim text.