US 6,211,705 B1 · Timed bistable circuit for high frequency applications

Abstract

A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Claims12

Dependent claims

A method for latching data in an integrated circuit having first and second input inverters, the method comprising:

receiving, at the first and second inverters respectively during a first sampling phase, a first and second signal input, wherein first and second input capacitances associated with the first and second inverters, respectively, are charged;
eliminating, during a second sampling phase, charge stored by a parasitic capacitance associated with the integrated circuit;
and
comparing, during an evaluation phase, the first and second signal inputs.

1 more element

Dependencies are inferred from the claim text.

Timed bistable circuit for high frequency applications

Life of this patent

Timed bistable circuit for high frequency applications

Life of this patent

Abstract

Claims12