FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections

In a field programmable gate array device (FPGA) having a user-configurable interconnect network that includes a plurality of horizontal interconnect channels each with a diversified set of long-haul interconnect lines and shorter-haul interconnect lines, an embedded memory subsystem comprising:

• (a) a plurality of multi-ported memory blocks each arranged adjacent to a horizontal interconnect channel (HIC) of the interconnect network;
• wherein:
• (a.1) each multi-ported memory block includes a first, independently-addressable data port and a second, independently-addressable data port;
• (a.2) each of said first and second, independently-addressable data ports includes a respective address-capturing register that is connectable by user-configurable intercouplings to one or both of the long-haul interconnect lines and the shorter-haul interconnect lines for capturing a respective address signal in synchronism with a supplied, address-strobing signal;
• and
• (a.3) each of said first and second, independently-addressable data ports includes a respective, read data-capturing resister that is connectable by user-configurable intercouplings to at least the long-haul interconnect lines for capturing respective read data of the port independently of the address-strobing signal and for outputting the captured read data to the long-haul interconnect lines.

In an FPGA device having a plurality of variable grain, configurable logic blocks (VGB's) and VGB interconnect resources including lines of diversified continuous lengths for interconnecting said VGB's, an embedded memory subsystem comprising:

• a special interconnect channel, programmably couplable to said VGB interconnect resources:
• and
• a plurality of memory blocks wherein each memory block includes:
• (a) at least a first address-capturing register that is programmably couplable to said VGB interconnect resources by way of said special interconnect channel for receiving and capturing a respective first address signal supplied by way of said VGB interconnect resources and said special interconnect channel;
• and
• (a.1) address-strobing means for strobing the first address-capturing register by way of said VGB interconnect resources and said special interconnect channel, where said address-strobing can occur independently of data-capture strobing for corresponding data.

A method for use in an FPGA device having plural variable grain blocks (VGB's), configurable interconnect resources with continuous conductors of diversified lengths, and an embedded memory subsystem comprising a plurality of memory blocks situated for configurable coupling to the diversified interconnect resources, where the memory blocks each have at least one address input port and at least one data port, the address input port having a respective address-capturing register, said method comprising the steps of:

• (a) outputting a first address signal for conveyance by at least part of said interconnect resources to a respective first address-capturing register of an address input port of a given memory block;
• (b) outputting a first address-strobing signal for conveyance by at least part of said interconnect resources to the respective first address-capturing register to thereby capture the conveyed first address signal in the respective first address-capturing register of the given memory block;
• and
• (d) coupling the first address-strobing signal through delaying logic for thereby invoking a delay in outputting of a next address signal for conveyance by at least part of said interconnect resources to the respective first address-capturing register of the address input port of the given memory block, said invoked delay assuring that the first address signal is captured by the respective first address-capturing register before the outputting of said next address signal.

A method for configuring an FPGA device having plural variable grain blocks (VGB's), configurable interconnect resources, and an embedded memory subsystem comprising one or more memory blocks situated for configurable coupling via the configurable interconnect resources to the VGB's, where the memory blocks each have at least one registered address input port for receiving and storing supplied address bits, and where the memory blocks each further have at least one registered data output port for storing and outputting retrieved read-data, said method comprising the steps of:

• (a) defining a first route through said interconnect resources from an address signal sourcing circuit of the FPGA device to the at least one registered address input port;
• (b) defining a second route through said interconnect resources from an address clock sourcing circuit of the FPGA device to the at least one registered address input port;
• (c) defining a third route through said interconnect resources from the address clock sourcing circuit to an address-changing circuit of the FPGA device, the third route being configured such that a new address signal can be produced by action of said address-changing circuit substantially at the same time or shortly after an address clock signal of the address clock sourcing circuit clocks the at least one registered address input port, said new address signal being produced so as to not interfere with a current address signal captured by the registered address input port;
• and
• (d) defining a fourth route through said interconnect resources from a read clock sourcing circuit of the FPGA device to the at least one registered data output port.

A method for producing configuration signals for configuring an FPGA device having plural variable grain blocks (VGB's) configurable interconnect resources, and an embedded memory subsystem comprising one or more memory blocks situated for configurable coupling via the configurable interconnect resources to the VGB's, where the memory blocks each have at least one registered address input port for receiving and storing supplied address bits in response to a supplied address-strobing signal, and where the memory blocks each have at least one registered data output port for storing and outputting retrieved read-data, the storing of the retrieved read-data being in response to a supplied data-strobing signal, said method comprising the steps of:

• (a) inputting a design definition;
• (b) searching the input design definition for the presence of one or more memory modules, address-sourcing modules, and data-using modules that will cooperate to perform a memory read or memory write operation;
• and
• (c) encouraging the creation in the configured FPGA of a shared signal route that transmits an address-strobing clock signal to the registered address input port and that transmits an address-change allowing signal to one or more of the address-sourcing modules and that transmits a data-strobing signal to one or more of the registered data output ports.

A field programmable gate array (FPGA) device comprising:

• (a) a plurality of configurable logic blocks (CLB's);
• (b) configurable CLB interconnect resources for configurably interconnecting said CLB's;
• (c) a memory subsystem comprising:
• (c.1) a plurality of independently-usable memory blocks each having:
• (c.1a) a shared array of memory cells;
• (c.1b) a first port unit coupled to the shared array and including a respective first data output port and a first address input port;
• (c.1c) a second port unit coupled to the shared array and including a respective second data output port and a second address input port, wherein the first and second port units can simultaneously access the shared array of memory cells;
• (c.1d) first and second address-capturing registers respectively coupled to the first and second address input ports, each address-capturing register having address and clock inputs and an address output;
• (c.1e) first and second read-data capturing registers respectively coupled to the first and second data output ports, each data capturing register having data and clock inputs and a data output;
• (c.2) a configurable, first special interconnect channel that is programmably couplable to said CLB interconnect resources,
• (c.2a) said first special interconnect channel extending adjacent to a respective first group of said memory blocks;
• (c.2b) said first special interconnect channel being further programmably couplable to the respective clock inputs of the first and second address-capturing registers of said first group of memory blocks such that the respective clock inputs of the first and second address-capturing registers of one or more memory blocks in the first group can be respectively driven by at least a first address-strobing signal which is transmitted by way of the first special interconnect channel;
• and
• (c.2c) said first special interconnect channel being further programmably couplable to the respective clock inputs of the first and second read-data capturing registers of said first group of memory blocks such that the respective clock inputs of the first and second read-data capturing registers of one or more memory blocks in the first group can be respectively driven by independent first and second data-strobing signals which are transmitted by way of the first special interconnect channel.

A method of configuring a field programmable gate array (FPGA) device where the FPGA device comprises:

• (0.1) a plurality of configurable logic blocks (CLB's);
• (0.2) configurable CLB interconnect resources for configurably interconnecting said CLB's;
• (0.3) a memory subsystem comprising:
• (0.31) a plurality of independently-usable memory blocks each having:
• (0.31a) a shared array of memory cells;
• (0.31b) a first port unit coupled to the shared array and including a respective first data output port and a first address input port;
• (0.31c) a second port unit coupled to the shared array and including a respective second data output port and a second address input port;
• (0.31d) at least one address-capturing registers respectively coupled to one of the first and second address input ports, the at least one address-capturing register having address and clock inputs and an address output;
• (0.31e) at least one read-data capturing register respectively coupled to one of the first and second data output ports, the at least one data capturing register having data and clock inputs and a data output;
• (0.32) a configurable, special interconnect channel that is programmably couplable to said CLB interconnect resources,
• (0.32a) said special interconnect channel extending adjacent to said memory blocks;
• (0.32b) said special interconnect channel being further programmably couplable to the respective clock inputs of the at least one address-capturing registers of said memory blocks such that the respective clock inputs of the at least one address-capturing registers of one or more of the memory blocks can be respectively driven by at least a first address-strobing signal which is transmittable by way of the special interconnect channel;
• and
• (0.32c) said special interconnect channel being further programmably couplable to the respective clock inputs of the at least one read-data capturing registers of said memory blocks such that the respective clock inputs of the at least one read-data capturing registers of one or more of the memory blocks can be respectively driven by a data-strobing signals which is transmittable by way of the special interconnect channel;
• said FPGA configuring method comprising:
• (a) configuring the special interconnect channel to supply an address-strobing signal to the clock input of an address-capturing register of a given one of said memory blocks;
• and
• (b) configuring the special interconnect channel to supply a data-strobing signal to the clock input of a read-data capturing register of the given one of said memory blocks such that the supplied address-strobing and data-strobing signals can be independent of one another.

A field programmable gate array (FPGA) device comprising:

• (a) a plurality of configurable logic blocks (CLB's);
• (b) configurable CLB interconnect resources for configurably interconnecting said CLB's;
• (c) a memory subsystem comprising:
• (c.1) a plurality of independently-usable memory blocks each having:
• (c.1a) a shared array of memory cells;
• (c.1b) a first port unit coupled to the shared array and including a respective first data output port and a first address input port;
• (c.1c) a second port unit coupled to the shared array and including a respective second data output port and a second address input port, wherein the first and second port units can access respectively addressed parts of the shared array of memory cells;
• (c.1d) first and second address-capturing registers respectively coupled to the first and second address input ports, each address-capturing register having address and clock inputs and an address output;
• (c.1e) first and second read-data capturing registers respectively coupled to the first and second data output ports, each data capturing register having data and clock inputs and a data output;
• (c.2) a configurable, first special interconnect channel that is programmably couplable to said CLB interconnect resources,
• (c.2a) said first special interconnect channel extending adjacent to a respective first group of said memory blocks;
• (c.2b) said first special interconnect channel being further programmably couplable to the respective clock inputs of the first and second address-capturing registers of said first group of memory blocks such that the respective clock inputs of the first and second address-capturing registers of one or more memory blocks in the first group can be respectively driven by at least a first address-strobing signal which is transmitted by way of the first special interconnect channel;
• and
• (c.2c) said first special interconnect channel being further programmably couplable to the respective clock inputs of the first and second read-data capturing registers of said first group of memory blocks such that the respective clock inputs of the first and second read-data capturing registers of one or more memory blocks in the first group can be respectively driven by one or more data-strobing signals which are independent of the first address-strobing signal thereby allowing read-data-capture and address-capture operations by respective ones of the read-data capturing registers and address-capturing registers to occur at different times, and wherein said one or more data-strobing signals are transmitted by way of the first special interconnect channel.