Evaluation apparatus and fabrication system for semiconductor
AssigneeKabushiki Kaisha Toshiba
InventorsKazuya Matsuzawa, Yukihito Oowaki
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AssigneeKabushiki Kaisha Toshiba
InventorsKazuya Matsuzawa, Yukihito Oowaki
Estimating the term…
The present invention comprises a SCM measuring apparatus and a control section. A control section adjusts shape data of a probe tip initially inputted based on SCM measurement for a standard specimen and a simulated result by the measuring apparatus, and then performs the SCM measurement by a standard specimen, and then on the basis of the measuring result, a impurity distribution is assumed. Next, the impurity distribution is adjusted so that the CV property calculated by the SCM simulation coincides with the CV property measured by the SCM measuring apparatus, and then the CV property is calculated again. The impurity distribution in case both of the CV properties coincide with each other is determined as a definitive impurity distribution. The definitive impurity distribution is outputted to a display apparatus, a printer, and so on. Therefore, it is possible to analyze the impurity distribution with accuracy smaller than a width of the probe tip.
A semiconductor evaluation apparatus comprising SCM measuring means for measuring a CV property showing a relationship between a capacitance C between a probe tip and a specimen, and a voltage V supplied to the specimen via the probe tip, comprising:
A semiconductor fabrication system including a semiconductor fabrication apparatus, comprising:
A semiconductor evaluation apparatus comprising an AFM measuring means for analyzing surface shape of a specimen based on a force working between the specimen and a probe tip placed above the specimen, comprising:
A semiconductor fabrication system, including a semiconductor fabrication apparatus, comprising:
Dependencies are inferred from the claim text.