MOS transistor output circuits using PMOS transistors
AssigneeNortel Networks Limited
InventorStepan Iliasevitch
Life of this patent
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Abstract
A signal voltage converter converts a 0V to −5V input signal to a +5V to 0V output signal using PMOS transistors for both pull-up and pull-down of the output. Bipolar transistor level shifters and PMOS current mirrors are used to control the pull-up and pull-down transistors in conjunction with a clamp circuit. Output signal transitions are matched for both transition directions to reduce signal timing distortion, and this can be further enhanced by an optional circuit for supplying a controlled current for the clamp circuit.
Claims20
A MOS transistor output circuit having terminals for relatively positive, zero, and negative supply voltages, comprising:
- a first PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain connected to an output;
- a second PMOS transistor having a source connected to the output, a gate, and a drain connected to the zero supply voltage;
- at least one current mirror arrangement comprising at least a third PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain, the at least one current mirror arrangement being responsive to an input signal for controlling the first and third PMOS transistors via their gates to be simultaneously conductive and simultaneously non-conductive for respective logic levels of the input signal;
- a fourth PMOS transistor having a source coupled to the drain of the third PMOS transistor, a gate coupled to the zero voltage supply, and a drain coupled to the gate of the second PMOS transistor;
- and
- a clamp circuit coupled to the gate of the second PMOS transistor and responsive to the input signal for supplying a relatively positive or negative voltage to the gate of the second PMOS transistor, to render the second PMOS transistor respectively non-conductive or conductive, when the first and third PMOS transistors are respectively conductive and non-conductive.
A MOS transistor signal voltage converter having relatively positive, zero, and negative supply voltages for converting an input signal having logic levels represented by voltages at about the zero and negative supply voltages to an output signal having logic levels represented by voltages at about the positive and zero supply voltages, the converter comprising:
- a first PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain connected to an output for the output signal;
- a second PMOS transistor having a source connected to the output, a gate, and a drain connected to the zero supply voltage;
- at least one level shifter comprising an NPN bipolar transistor having a base coupled to the zero supply voltage, an emitter coupled to a signal path responsive to the input signal, and a collector;
- at least one current mirror arrangement coupled to the collector of the at least one level shifter and including at least a third PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain, the at least one current mirror arrangement being responsive to current conducted by the transistor of the at least one level shifter to control the first and third PMOS transistors via their gates to be simultaneously conductive and simultaneously non-conductive for respective logic levels of the input signal;
- a fourth PMOS transistor having a source coupled to the drain of the third PMOS transistor, a gate coupled to the zero voltage supply, and a drain coupled to the gate of the second PMOS transistor;
- and
- a clamp circuit coupled to the gate of the second PMOS transistor and responsive to the input signal for controlling the second PMOS transistor to be respectively non-conductive and conductive when the first and third PMOS transistors are respectively conductive and non-conductive.
Dependencies are inferred from the claim text.