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US 6,211,659 B1Granted
Cascode circuits in dual-Vt, BICMOS and DTMOS technologies
AssigneeIntel Corporation
InventorSurinder P. Singh
Life of this patent
Estimating the term…
Abstract
The various embodiments utilize cascode circuits in dual-threshold-voltage (dual-VT), BiCMOS and DTMOS technologies. The circuit topologies include cascode-connected transistors in the output branch of a current mirror and as a cascode amplifier. Such configurations are capable of both high output impedance and high output swing. The cascode circuits of the various embodiments are operable without separate gate-bias voltages for the cascode-connected transistors. The current mirrors can be used in circuits requiring a regulated current or other current mirroring applications. The current mirrors can further be used as active loads, such as an active load for an amplifier.
Claims33
A current mirror, comprising:
- a first output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a first threshold voltage, wherein the first source/drain terminal of the first output transistor is coupled to a first potential node;
- and
- a second output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a second threshold voltage, wherein the first source/drain terminal of the second output transistor is coupled to the second source/drain terminal of the first output transistor and the second source/drain terminal of the second output transistor is coupled to a second potential node, further wherein the second threshold voltage is higher than the first threshold voltage, the gate of the first output transistor is coupled to the gate of the second output transistor, and at least one of the first and second output transistors receives a body bias.
A current mirror, comprising:
- an enhancement mode output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a threshold voltage, wherein the first source/drain terminal of the enhancement mode output transistor is coupled to a first potential node;
- and
- a bipolar output transistor having a base, a collector and an emitter and having a turn-on voltage, wherein the collector of the bipolar output transistor is coupled to the second source/drain terminal of the enhancement mode output transistor and the emitter of the bipolar output transistor is coupled to a second potential node, further wherein the turn-on voltage of the bipolar output transistor is higher than the threshold voltage of the enhancement mode output transistor;
- wherein the gate of the enhancement mode output transistor is coupled to the base of the bipolar output transistor.
1 more element
A current mirror, comprising:
- a bipolar output transistor having a base, a collector and an emitter and having a turn-on voltage, wherein the collector of the bipolar output transistor is coupled to a first potential node;
- and
- an enhancement mode output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a threshold voltage, wherein the first source/drain terminal of the enhancement mode output transistor is coupled to the emitter of the bipolar output transistor and the second source/drain terminal of the enhancement mode output transistor is coupled to a second potential node, further wherein the threshold voltage of the enhancement mode output transistor is higher than the turn-on voltage of the bipolar output transistor;
- wherein the gate of the enhancement mode output transistor is coupled to the base of the bipolar output transistor.
1 more element
A current mirror, comprising:
- a reference branch, comprising:
- a first reference transistor having a gate, a first source/drain terminal and a second source/drain terminal;
- and
- an output branch, comprising:
- a first output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a first threshold voltage, wherein the first source/drain terminal of the first output transistor is coupled to a first potential node;
- and
- a second output transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a second threshold voltage, wherein the first source/drain terminal of the second output transistor is coupled to the second source/drain terminal of the first output transistor and the second source/drain terminal of the second output transistor is coupled to a second potential node, further wherein the second threshold voltage is higher than the first threshold voltage;
- wherein the gates of the first reference transistor, the first output transistor and the second output transistor are coupled to the first source/drain terminal of the first reference transistor;
- and
- wherein at least one of the first output transistor and the second output transistor receives a body bias.
7 more elements
A cascode amplifier, comprising:
- a first transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a first threshold voltage, wherein the first source/drain terminal of the first transistor is coupled to a load and an amplifier output in parallel, wherein the load is further coupled to a first potential node;
- and
- a second transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a second threshold voltage, wherein the first source/drain terminal of the second transistor is coupled to the second source/drain terminal of the first transistor and the second source/drain terminal of the second transistor is coupled to a second potential node, further wherein the second threshold voltage is higher than the first threshold voltage, still further wherein the gate of the first transistor is coupled to the gate of the second transistor and an amplifier input;
- wherein a body of the first transistor receives a positive bias.
1 more element
A cascode amplifier, comprising:
- a first transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a first threshold voltage, wherein the first source/drain terminal of the first transistor is coupled to a load and an amplifier output in parallel, wherein the load is further coupled to a first potential node;
- and
- a second transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a second threshold voltage, wherein the first source/drain terminal of the second transistor is coupled to the second source/drain terminal of the first transistor and the second source/drain terminal of the second transistor is coupled to a second potential node, further wherein the second threshold voltage is higher than the first threshold voltage, still further wherein the gate of the first transistor is coupled to the gate of the second transistor and an amplifier input;
- wherein a body of the second transistor receives a negative bias.
1 more element
A cascode amplifier, comprising:
- an enhancement mode transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a threshold voltage, wherein the first source/drain terminal of the enhancement mode transistor is coupled to a load and an amplifier output in parallel, wherein the load is further coupled to a first potential node;
- and
- a bipolar transistor having a base, a collector and an emitter and having a turn-on voltage, wherein the collector of the bipolar transistor is coupled to the second source/drain terminal of the enhancement mode transistor and the emitter of the bipolar transistor is coupled to a second potential node, further wherein the turn-on voltage of the bipolar transistor is higher than the threshold voltage of the enhancement mode transistor;
- wherein the gate of the enhancement mode transistor is coupled to the base of the bipolar transistor;
- and
- wherein the gate of the enhancement mode transistor and the base of the bipolar transistor are coupled to an amplifier input.
3 more elements
A cascode amplifier, comprising:
- a bipolar transistor having a base, a collector and an emitter and having a turn-on voltage, wherein the collector of the bipolar transistor is coupled to a load and an amplifier output in parallel, wherein the load is further coupled to a first potential node;
- and
- an enhancement mode transistor having a gate, a first source/drain terminal and a second source/drain terminal and having a threshold voltage, wherein the first source/drain terminal of the enhancement mode transistor is coupled to the emitter of the bipolar transistor and the second source/drain terminal of the enhancement mode transistor is coupled to a second potential node, further wherein the threshold voltage of the enhancement mode transistor is higher than the turn-on voltage of the bipolar transistor;
- wherein the gate of the enhancement mode transistor is coupled to the base of the bipolar transistor;
- and
- wherein the gate of the enhancement mode transistor and the base of the bipolar transistor are coupled to an amplifier input.
3 more elements
Dependencies are inferred from the claim text.