Resurf LDMOS device with deep drain region

#This invention relates to semiconductor devices and, more particularly, to a RESURF (REduced SURf ace Field) LDMOS (lateral double-diffused “metal” N-oxide-semiconductor) device having a deep buffer implant in the drain region and method of fabrication thereof.

#LDMOS devices are the devices of choice in the 20-60V range. LDMOS devices are very easy to integrate into a CMOS or BiCMOS process thereby facilitating the fabrication of control, logic, and power switches on a single chip. In the 20-60V range, optimized LDMOS devices are also much more efficient in terms of on-state voltage and switching losses than power bipolar junction transistors or other hybrid MOSbipolar devices.

#Optimized LDMOS design seeks to provide power switches with very low specific on-state resistance (Rsp) while maintaining high switching speed. A low Rsp helps reduce power losses as well as the size of the die. RESURF LDMOS or RLDMOS devices are very attractive in this respect as they offer very good trade-off between Rsp and breakdown voltage (BV) capability compared to non-RLDMOS devices. RLDMOS devices use the Reduced Surface electric field phenomenon to increase the drift region doping for a given breakdown voltage. The increased drift region doping causes reduction in the drift region resistance leading to an overall lower Rsp for the device.

#In the drawings:

#FIG. 1 is a cross-sectional elevation view of a RESURF LDMOS transistor according to the prior art;

#FIG. 2 shows the measured BV (breakdown voltage) curve at room temperature for a device according to FIG. 1;

#Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.

#FIG. 1 shows an RLDMOS transistor 10 according to the prior art. Transistor 10 is fabricated in a p− epitaxial layer 14 formed over p+substrate 12. Transistor 10 includes a p well 16 in epitaxial layer 14. An n+source region 22 and p+ backgate contact region 20 are formed in p well 16. Transistor 10 also includes n+ drain region 24 and an n type RESURF region 18 formed in epitaxial layer 14. RESURF region 18 is self-aligned to LOCOS field oxide region 28. A gate oxide layer 26 is formed at the face of epitaxial layer 14. Polysilicon gate 30 extends over gate oxide layer 26 and a portion of LOCOS field oxide region 28.

#FIG. 2 shows the measured BV (breakdown voltage) curve at room temperature for a device according to FIG. 1 having a distance L=3.3 microns, distance M=2.0 microns, and device area=8e−3 cm2 with p- epi doping and n- type resurf implant dose chosen to obtain about 45V BVdss (drain-source breakdown voltage with gate shorted to source).