Semiconductor memory array with buried drain lines and processing methods therefor

A semiconductor memory array, comprising:

• a substrate;
• a plurality of memory cell field effect transistors formed on said substrate and arranged thereon into rows and columns of transistors, each transistor including,
• a channel region interposed between drain and source regions,
• a floating gate formed over said substrate and overlying at least a portion of said channel, said floating gate being separated from said channel by a first insulating layer, said floating gate including a pair of ridges formed on a top surface thereof, said ridges having opposing inner walls that are substantially vertical to the plane of said substrate, each of said ridges also having a sharp edge formed on a top surface thereof, and
• a control gate formed over said substrate and said floating gate, and overlying at least a portion of said channel, said control gate being separated from said floating gate by a second insulating layer,
• each of said edges for facilitating electron tunneling from said floating gate to said control gate during memory erase operations;
• a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns;
• a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns;
• and
• a plurality of elongated conductive lines formed over said substrate that electrically connect in common the control gates of transistors in respective rows.