US 6,211,534 B1Granted

Thin film transistor array and method for fabricating the same

AssigneeNEC Corporation

InventorSeiichi Matsumoto

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Abstract

A TFT array for a liquid crystal display device in which inferiority due to electrification or abnormal discharge during fabrication process can be decreased. The TFT array comprises TFTs for display each connected to a respective one of pixel electrodes disposed in a matrix, gate wirings, signal lines, a common conductor line on the gate wiring side, a common conductor line on the signal line side, nonlinear elements respectively disposed between the gate wirings and the common conductor line on the gate wiring side and between the signal lines and the common conductor line on the signal line side. A gate electrode of a TFT in each of the nonlinear elements is formed separately from the corresponding common conductor line and is electrically coupled thereto via contact holes and a third conductor layer. A source/drain electrode of a TFT in each of the nonlinear elements is formed seprately from the corresponding common conductor line and is electrically coupled thereto via contact holes and the third conductor layer.

Claims9

Dependent claims

A thin film transistor array comprising:

a substrate;
a plurality of pixel electrodes formed on said, substrate and disposed in a matrix having rows and columns;
a plurality of thin film transistors (TFTs) for display which are formed on said substrate and each of which is connected to a corresponding one of said pixel electrodes;
a plurality of gate wirings which are formed on said substrate, which are formed by a first conductor layer, each of which is disposed along every row of said pixel electrodes and each of which is used for supplying a gate signal to said TFTs in a corresponding row;
a plurality of signal lines which are formed on said substrate, which are formed by a second conductor layer, each of which is disposed along every column of said pixel electrodes, and each of which is used for supplying a data signal to said TFTs in a corresponding column;
a common conductor line on the gate wiring side formed on said substrate and extending in a direction perpendicular to the direction of extension of said gate wirings;
a common conductor line on the signal line side formed on said substrate and extending in a direction perpendicular to the direction of extension of said signal lines;
nonlinear elements which are respectively disposed between one end of each of said gate wirings and said common conductor line on the gate wiring side and between one end of each of said signal lines and said common conductor line on the signal line side, and each of which comprises a plurality of TFTs;
wherein one of gate electrodes of said TFTs in each of said nonlinear elements disposed between one ends of said gate wirings and said common conductor line on the gate wiring side is formed separately from said common conductor line on the gate wiring side;
wherein one of source/drain electrodes of said TFTs in each of said nonlinear elements disposed between one ends of said signal lines and said common conductor line on the signal line side is formed separately from said common conductor line on the signal line side;
wherein said one of the gate electrodes of said TFTs in each of said nonlinear elements disposed between one ends of said gate wirings and said common conductor line on the gate wiring side is electrically coupled to said common conductor line on the gate wiring side via contact holes formed in an insulating film formed on said first and second conductor layers and via a third conductor layer;
and
wherein said one of the source/drain electrode of said TFTs in each of said nonlinear elements disposed between one ends of said signal lines and said common conductor line on the signal line side is electrically coupled to said common conductor line on the signal line side via contact holes formed in said insulating film formed on said first and second conductor layers and via said third conductor layer.

10 more elements

A thin film transistor array comprising:

a substrate made of transparent and insulating material;
a plurality of transparent pixel electrodes formed on said substrate and disposed in a matrix having rows and columns;
a plurality of thin film transistors (TFTs) for display which are formed on said substrate and each of which is connected to a corresponding one of said transparent pixel electrodes;
a plurality of gate wirings which are formed on said substrate, which are formed by a first conductor layer, each of which is disposed along every row of said transparent pixel electrodes and each of which is used for supplying a gate signal to said TFTs in a corresponding row;
a plurality of signal lines which are formed on said substrate, which are formed by a second conductor layer, each of which is disposed along every column of said pixel electrodes, and each of which is used for supplying a data signal to said TFTs in a corresponding column;
a plurality of gate terminals which are formed on said substrate and each of which is formed integrally with and at one end of respective one of said gate wirings;
a plurality of signal terminals which are formed on said substrate and each of which is formed integrally with and at one end of respective one of said signal lines;
a first group of nonlinear elements which are disposed on said substrate and disposed at one ends of said gate terminals and each of which has a first TFT and a second TFT, both a gate electrode and a drain electrode of said first TFT being connected to said gate terminal, and the drain electrode and source electrode of said first TFT being connected to a source electrode and a drain electrode of said second TFT, respectively;
a common conductor line on the gate wiring side which is formed on said substrate, which extends in a direction perpendicular to the direction of extension of said gate wirings, and which is electrically connected to both the gate electrode and the drain electrode of said second TFT of corresponding one of said first group of nonlinear elements;
a second group of nonlinear elements which are disposed on said substrate and disposed at one ends of said signal terminals and each of which has a third TFT and a fourth TFT, both a gate electrode and a drain electrode of said third TFT being connected to said signal terminal, and the drain electrode and source electrode of said third TFT being connected to a source electrode and a drain electrode of said fourth TFT, respectively;
a common conductor line on the signal line side which is formed on said substrate, which extends in a direction perpendicular to the direction of extension of said signal lines, and which is electrically connected to both the gate electrode and the drain electrode of said fourth TFT of corresponding one of said second group of nonlinear elements;
wherein said gate electrode of said second TFT in each of said first group of nonlinear elements is formed by said first conductor layer and is isolated from other portions of said first conductor layer;
wherein said common conductor line on the gate wiring side is formed by said second conductor layer;
wherein said gate electrode of said second TFT in each of said first group of nonlinear elements is electrically coupled to said common conductor line on the gate wiring side via contact holes formed in an insulating film formed on said first and second conductor layers and via a third conductor layer;
wherein said source/drain electrode of said fourth TFT in each of said second group of nonlinear elements is firmed by said second conductor layer and is isolated from other portions of said second conductor layer;
wherein said common conductor line on the signal line side is formed by said first conductor layer;
and
wherein said source/drain electrode of said fourth TFT in each of said second group of nonlinear elements is electrically coupled to said common conductor line on the signal line side via contact holes formed in said insulating film formed on said first and second conductor layers and via said third conductor layer.

15 more elements

A thin film transistor array comprising:

a substrate made of transparent and insulating material;
a plurality of transparent pixel electrodes formed on said substrate and disposed in a matrix having rows and columns;
a plurality of thin film transistors (TFTs) for display which are formed on said substrate and each of which is connected to a respective one of said transparent pixel electrodes;
a plurality of signal lines which are formed on said substrate, which are formed by a first conductor layer, each of which is disposed along every column of said pixel electrodes, and each of which is used for supplying a data signal to said TFTs in a corresponding column;
a plurality of gate wirings which are formed on said substrate, which are formed by a second conductor layer, each of which is disposed along every row of said transparent pixel electrodes and each of which is used for supplying a, gate signal to said TFTs in a corresponding row;
a plurality of gate terminals which are formed on said substrate and each of which is formed integrally with and at one end of respective one of said gate wirings;
a plurality of signal terminals which are formed on said substrate and each of which is formed integrally with and at one end of respective one of said signal lines;
a first group of nonlinear elements which are disposed on said substrate and disposed at one ends of said gate terminals and each of which has a first TFT and a second TFT, both a gate electrode and a drain electrode of said first TFT being connected to said gate terminal, and the drain electrode and source electrode of said first TFT being connected to a source electrode and a drain electrode of said second TFT, respectively;
a common conductor line on the gate wiring side which is formed on said substrate, which extends in a direction perpendicular to the direction of extension of said gate wirings, and which is electrically connected to both the gate electrode and the drain electrode of said second TFT of corresponding one of said first group of nonlinear elements;
a second group of nonlinear elements which are disposed on said substrate and disposed at one ends of said signal terminals and each of which has a third TFT and a fourth TFT, both a gate electrode and a drain electrode of said third TFT being connected to said signal terminal, and the drain electrode and source electrode of said third TFT being connected to a source electrode and a drain electrode of said fourth TFT, respectively;
a common conductor line on the signal line side which is formed on said substrate, which extends in a direction perpendicular to the direction of extension of said signal lines, and which is electrically connected to both the gate electrode and the drain electrode of said fourth TFT of corresponding one of said second group of nonlinear elements;
wherein said gate electrode of said second TFT in each of said first group of nonlinear elements is formed by said second conductor layer and is isolated from other portions of said second conductor layer;
wherein said common conductor line on the gate wiring side is formed by said first conductor layer;
wherein said gate electrode of said second TFT in each of said first group of nonlinear elements is electrically coupled to said common conductor line on the gate wiring side via contact holes formed in an insulating film formed on said first and second conductor layers and via a third conductor layer;
wherein said source/drain electrode of said fourth TFT in each of said second group of nonlinear elements is formed by said first conductor layer and is isolated from other portions of said first conductor layer;
wherein said common conductor line on the signal line side is formed by said second conductor layer;
and
wherein said source/drain electrode of said fourth TFT in each of said second group of nonlinear elements is electrically coupled to said common conductor line on the signal line side via contact holes formed in said insulating film formed on said first and second conductor layers and via said third conductor layer.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/310,574Filed 12 May 1999
Priority: JP 10-15059214 May 1998
Granted: 3 Apr 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G02F 1/136204
Active matrix addressed cells: arrangements to prevent high voltage or static electricity failures
H10D 86/40
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G02F
Optical devices or arrangements for the control of light by modification of