US 6,209,121 B1 · Method and system for improving delay error

Abstract

In a delay error improving process of a logic circuit, delay performance is certainly improved by maintaining layout and wiring path after completion of layout and wiring. A path delay is calculated by a circuit delay period calculating portion using an actual wiring information after wiring process. By the critical path extracting portion, a path not satisfying a delay performance and critical path is extracted. The cell on the critical path is re-arranged with replacing the cell having different delay performance with the same function. The overlap of the replaced cell with the other cell is solved by moving the cell. By the partial re-wiring portion, wiring connected to the replaced cell and the cells moved for overlap solving within the partial wiring region are re-wired and the layout and the wiring path of the cells not influenced by the cell replacement are maintained.

Claims10

Dependent claims

A method for reducing delay error in a circuit comprising the steps of:

performing delay analysis on a wired circuit using an actual wiring information;
determining an object cell for replacement based on the delay analysis;
replacing the object cell with a delay improving cell having an improved delay characteristic;
eliminating an overlap of cells caused by replacing the object cell with the delay improving cell;
re-wiring said delay improving cell and cells which overlapped the delay improving cells;
performing delay analysis with respect to a signal path on which the delay improving cell is present;
and
displaying a message indicating non-completion of delay improvement when a calculated path delay exceeds path delay restriction value and no other cell is present in the signal path.

5 more elements

A system for reducing delay error in a circuit comprising:

a delay analyzing portion for performing delay analysis on a wired circuit using an actual wiring information;
a cell extracting portion for determining an object cell for replacement based on the delay analysis;
a cell replacing portion for replacing the object cell with a delay improving cell having an improved delay characteristic;
an overlap eliminating portion for eliminating an overlap of calls caused by replacing the object cell with the delay improving cell;
a re-wiring portion for re-wiring for said delay improving cell and cells which overlapped the delay improving cell;
a path delay re-calculating portion for re-calculating a path delay of a signal path on which the replaced cell is present after said re-wiring portion re-wires said delay improving cell and said cells which overlapped the delay improving cell;
and
a displaying portion for displaying of a message indicating non-completion of delay improvement when a calculated path delay exceeds a delay restriction value after replacing said object cell and no other cell is present in the same path.

5 more elements

Dependencies are inferred from the claim text.

Method and system for improving delay error

Life of this patent

Method and system for improving delay error

Life of this patent

Abstract

Claims10