Apparatus and method for synthesizing module

Abstract

A functional-level processing unit converts a data path diagram into logic circuit data. A logic-level processing unit specifies cells in a data path circuit based on the logic circuit data. A synthesis processing unit uses geometrical functions of the cells which have been parameterized by delays thereof, thereby synthesizing a layout module for the data path circuit based on the logic circuit data used to specify the cells and on a floorplan for the module. The synthesis processing unit also obtains a geometrical function parameterized by delay for the layout module. By synthesizing a layout module using the geometrical functions of the cells, which have been parameterized by the delays thereof, the geometry of the layout module can be optimized with high accuracy. In addition, by generating a geometrical function for the layout module, it becomes easier to establish a linkage to the upper process of design.

Dependencies are inferred from the claim text.