Code synchronization decision circuit of Viterbi decoder

Abstract

A code synchronization decision circuit of Viterbi decoder including a trigger signal generator that produces a trigger signal every time a symbol counter counts a predetermined number of symbols defined externally. A second comparator compares, in response to the trigger signal, the number of errors of symbols counted by an error counter with a threshold value that is externally set, and supplies a masking signal generator with a synchronization signal or a slip signal in response of the compared result. The masking signal generator, in response to the signals, generates a masking signal for suspending the operation of the error counter and symbol counter for a time period, during which unsuitable codes will be supplied to the code synchronization decision circuit from a re-encoder of the Viterbi decoder as one of compared values for detecting symbol errors. This makes it possible for a user to set the threshold value and the number of symbols to be counted with ease, and to implement a code synchronization decision circuit of a Viterbi decoder capable of saving power.

Dependencies are inferred from the claim text.