US 6,209,086 B1 · Method and apparatus for fast response time interrupt control in a pipelined data processor

Abstract

In a fast response time pipelined data processor, an interrupt control device stores the interrupt service routine address or the target address of a branch instruction, as applicable, in a register. If an interrupt occurs while the pipelined data processor is processing a branch instruction, the branch instruction target address stored in the register is used as the return address, and is stored in a working space, so that the interrupt can be processed immediately. Similarly, if an interrupt occurs while the pipelined data processor is processing a prior interrupt or exception, and the first instruction of the interrupt service routine of the previous interrupt has not yet reached the memory access stage, the interrupt service routine as address of the previous interrupt stored in the register is used as the return address, and is stored in the working space, so that the next interrupt can be processed immediately.

Claims10

Dependent claims

A method for controlling interrupts and exceptions in a fast response time pipelined processor, comprising thc following steps;

a) if a pipeline processing instruction cycle begins with a branch instruction, and said branch instruction has reached an instruction boundary, said instruction boundary being a memory access stage, and a branch is taken, or if an instruction located at a target address of a branch instruction has not yet reached an instruction boundary, storing said target address of said branch instruction at a first part of a working space,
otherwise, storing a first return address of a first interrupt or exception at said first part of said working space,
b) fetching a service routine starting address of said first interrupt/exception and executing a first instruction of said service routine at said starting address,
c) completing the execution of said first interrupt/exception service routine, and
d) returning to either said target address of said branch instruction or said first interrupt/exception starting address, whichever address having been previously stored at said first part of said working space,
wherein said fast response time pipelined processor processes said interrupts and exceptions within a pipeline stage at the time said interrupts and exceptions occur.

3 more elements

A processor control apparatus for controlling interrupts and exceptions which are processed in a first pipeline stage of a fast response time pipelined processor, comprising:

a) a processor control unit, having a first output port and a second output port,
b) a storage device having an input and an output,
c) a multiplexer having a select input, a plurality of return address inputs, and an output,
wherein when said processor control unit receives a branch taken signal of a branch instruction at a first clock, said processor control unit outputs a branch target address of said branch instruction from said first output port to said storage device input,
wherein when said processor control unit receives an interrupt/exception at said first clock, said processor control unit outputs a select signal at a second clock front said second output port to said select input of said multiplexer, said select signal designating a particular one of said plurality of return address inputs as a return address of said interrupt/exception, said processor control unit also fetching a starting address of a service routine of said interrupt/exception at said second clock, said processor control unit then outputting said starting address from said first output port to said storage device input, and
wherein said multiplexer, in accordance with said select signal designation, selects at one of said plurality of return address inputs either:
said branch target address or said interrupt/exception start address from said output of said storage device, or
a program counter value of said first pipeline stage, when an interrupt/exception occurs in the absence of a branch taken signal and said pipeline processor processes said interrupt/exception as a trap type exception, or
a program counter value of a second pipeline stage, when an interrupt/exception occurs in the absence of a branch taken signal and said pipeline processor processes said interrupt/exception as a fault type exception,
said multiplexer then outputting said selected return address of said interrupt/exception service routine.

7 more elements

Dependencies are inferred from the claim text.

Method and apparatus for fast response time interrupt control in a pipelined data processor

Life of this patent

Method and apparatus for fast response time interrupt control in a pipelined data processor

Life of this patent

Abstract

Claims10