US 6,209,084 B1Granted

Dependency table for reducing dependency checking hardware

AssigneeAdvanced Micro Devices, Inc.

InventorsMuralidharan S. Chinnakonda, Thang M. Tran, Wade A. Walker

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Abstract

A dependency table stores a reorder buffer tag for each register. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. The dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested. If a narrow-to-wide dependency is detected the instruction is stalled until the instruction indicated in the dependency table retires.

Claims18

Dependent claims

A superscalar microprocessor comprising:

a first decode unit configured to decode a first instruction and to convey a first source operand specifier to a reorder buffer, and wherein said first source operand specifier is identified by said first instruction;
a second decode unit configured to decode a second instruction concurrent with said first decode unit decoding said first instruction, wherein said second decode unit is further configured to convey a second source operand specifier to said reorder buffer, and wherein said second source operand specifier is identified by said second instruction;
said reorder buffer coupled to said first decode unit and said second decode unit, wherein said reorder buffer is configured to receive said first and second source operand specifiers, and wherein said reorder buffer is configured to assign tags to a first source operand corresponding to said first source operand specifier and a second source operand corresponding to said second source operand specifier in accordance with dependency information stored in a dependency table included within said reorder buffer, and wherein said dependency information includes a set of tags and a set of widths, and wherein said reorder buffer assigns a first one of said set of tags to said first source operand if said first source operand specifier identifies a first register corresponding to said first one of said set of tags and said first source operand is a second portion of said first register included within a first portion of said first register identified by a first one of said set of widths corresponding to said first one of said set of tags, and wherein said reorder buffer assigns a second one of said set of tags to said second source operand if said second source operand specifier identifies a second register corresponding to said second one of said set of tags and said second source operand is a fourth portion of said second register included within a third portion of said second register identified by a second one of said set of widths corresponding to said second one of said set of tags, and wherein said first one of said set of tags identifies the most recent instruction in program order to update said first register, and wherein said second one of said set of tags identifies the most recent instruction in program order to update said second register;
and
a first reservation station coupled to receive said first one of said set of tags assigned to said first source operand;
and
a second reservation station coupled to receive said second one of said set of tags assigned to said second source operand.

4 more elements

A microprocessor comprising:

a decode unit configured to decode an instruction and to convey a source operand specifier to a reorder buffer, said source operand specifier identifying a source operand of said instruction;
a plurality of registers;
and
said reorder buffer coupled to said decode unit to receive said source operand specifier and further coupled to said plurality of registers, wherein said reorder buffer includes a dependency table storing a plurality of tags and a plurality of widths, each of said plurality of widths corresponding to a respective one of said plurality of tags, each of said plurality of tags corresponding to a respective one of said plurality of registers, and wherein said reorder buffer is configured to assign a first tag of said plurality of tags to said source operand if:
(i) said source operand specifier identifies a first register of said plurality of registers, said first register corresponding to said first tag, and (ii) said source operand is a second portion of said first register included within a first portion of said first register identified by a first width of said plurality of widths, said first width corresponding to said first tag, and wherein said first tag identifies a most recent instruction in program order to update said first register.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/566,216Filed 5 May 2000 · division
Priority: 17 May 1996
Granted: 27 Mar 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F 9/30112
Register structure: comprising data of variable length
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding