Processor having selectable exception handling modes

A microprocessor, comprising:

• means for programming indicia to select between a first mode of exception handling and a second mode of exception handling;
• means for executing a series of pipelined floating point instructions;
• means for issuing said series of pipelined floating point instructions to said execution means in said first mode of exception handling in which issuance of a next instruction in said series of pipelined floating point instructions is delayed until said execution means completes execution of a preceding instruction in said series of pipelined floating point instructions;
• and
• means for issuing said series of pipelined floating point instructions to said execution means in said second mode of exception handling in which said next instruction in said series of pipelined floating point instructions is issued before said execution means completes execution of said preceding instruction in said series of pipelined floating point instructions.

A microprocessor, comprising:

• a CPU core;
• a floating point unit, coupled to said CPU core, said floating point unit executing floating point instructions issued by said CPU core;
• and
• a register set having a control bit for controlling issuance of floating point instructions by said CPU core to said floating point unit, the microprocessor operating in a first mode exception handling when said control bit is set and operating in a second mode of exception handling if said control bit is unset;
• wherein said CPU core issues a next floating point instruction to said floating point unit prior to said floating point unit completing execution of a preceding floating point instruction if said microprocessor is operating in said second mode.

A computer, comprising:

• a system bus;
• a memory subsystem;
• and
• a microprocessor;
• said memory subsystem and said microprocessor coupled to said system bus for bidirectional exchanges of address, data and control signals therebetween;
• said microprocessor including:
• a CPU core;
• a floating point unit, coupled to said CPU core, said floating point unit executing floating point instructions issued by said CPU core;
• and
• a register set having a control bit for controlling issuance of floating point instructions by said CPU core to said floating point unit, the microprocessor operating in a first mode of exception handling when said control bit is set and operating in a second mode of exception handling if said control bit is unset;
• wherein said CPU core issues a next floating point instruction to said floating point unit prior to said floating point unit completing execution of a preceding floating point instruction if said microprocessor is operating in said second mode.