Apparatus and method for optimizing execution of push all/pop all instructions

An apparatus in a microprocessor for accessing a stack, comprising:

• translation logic, configured to receive a macro instruction directing the microprocessor to store/retrieve multiple operands to/from the stack, and to decode said macro instruction into an associated micro instruction sequence directing the microprocessor to access said multiple operands, wherein accesses to two of said multiple operands are grouped together into a combined access, said associated micro instruction sequence comprising:
• a plurality of double access micro instructions, each of said plurality of double access micro instructions directing the microprocessor to access a pair of said multiple operands;
• access alignment logic, coupled to said translation logic, configured to indicate alignment of said two of said multiple operands for the combined access;
• and
• data access logic, coupled to said translation logic, configured to receive said associated micro instruction sequence, and to accomplish the combined access;
• wherein the combined access is precluded when said access alignment logic indicates that said two of said multiple operands are misaligned and the combined access is allowed when said access alignment logic indicates that said two of said multiple operands are aligned.

An apparatus in a microprocessor for accessing multiple data entities in a stack, the apparatus comprising:

• a shadow stack pointer, configured to monitor a stack pointer in the microprocessor, and to indicate a top of stack associated with a macro instruction prior to execution of said macro instruction;
• an instruction decoder, coupled to said shadow stack pointer, for translating a push all/pop all macro instruction into double push/pop micro instructions and single push/pop micro instructions directing the microprocessor to access the multiple data entities in the stack;
• and
• a sequencer, coupled to said instruction decoder, configured to produce an order of said double push/pop micro instructions and said single push/pop micro instructions so that grouped aligned data entities are accessed by said double push/pop micro instructions.

A method in a microprocessor for executing a push all instruction or a pop all instruction to access multiple stack operands, comprising:

• a) reading a stack pointer to determine alignment of a pair of the multiple operands, said reading comprising:
• i) monitoring a stack pointer in the microprocessor to ascertain a current top of stack address prior to execution of the push all instruction or the pop all instruction;
• ii) estimating a new top of stack address based upon successful execution of the push all instruction or the pop all instruction;
• and
• iii) ascertaining alignment of a pair of the multiple operands using the new top of stack address provided by said estimating;
• and
• b) for the pair of the multiple operands which is determined to be aligned by a), combining the accesses to both operands in the pair into a single access, the single access being prescribed by a double push micro instruction or a double pop micro instruction.