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AssigneeInternational Business Machines Corporation
InventorsJames Allan Kahle, Donald Emil Waldecker
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A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an order consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.
A method for enhanced instruction dispatch efficiency in a superscalar processor system which can fetch an application specified ordered sequence of scalar instructions and simultaneously dispatch a group of said scalar instructions to a plurality of execution units, said method comprising the steps of:
A system for enhanced instruction dispatch efficiency in a superscalar processor system which can fetch an application specified ordered sequence of scalar instructions and simultaneously dispatch a group of said scalar instructions to a plurality of execution units, said system comprising:
Dependencies are inferred from the claim text.