Constant reconstruction processor that supports reductions in code size and processing time

A processor for executing operations based on instructions, the processor comprising:

• an instruction register for storing an instruction;
• first constant storage means including a first storage area;
• second constant storage means including a second storage area;
• decoding means for decoding the instruction stored in the instruction register and for giving an indication of one of four cases listed below—
• (1) a first case where the instruction includes a first constant to be stored into the first constant storage means,
• (2) a second case where the instruction includes a second constant to be stored into the second constant storage means,
• (3) a third case where a constant stored in the first constant storage means is to be used in an operation, and
• (4) a fourth case where a constant stored in the second constant storage means is to be used in an operation;
• constant transfer means for storing first state data showing whether a constant has been read from the first constant storage means and second state data showing whether a constant has been read from the second constant storage means, and for operating as follows
• (a) when the decoding means indicates the first case and the first state data shows that a constant has been read from the first constant storage means, the constant transfer means clears the first storage region, transfers the first constant from the instruction register to the first constant storage means, and sets the first state data to show that a constant has not been read from the first constant storage means,
• (b) when the decoding means indicates the first case and the first state data shows that a constant has not been read from the first constant storage means, the constant transfer means transfers the first constant from the instruction register to the first constant storage means without deleting a valid constant that is stored in the first constant storage means, links the first constant and the valid constant in the first constant storage means, and sets a linking result as a new valid constant,
• (c) when the decoding means indicates the second case and the second state data shows that the constant has been read from the second constant storage means, the constant transfer means clears the second storage region, transfers the second constant from the instruction register to the second constant storage means, and sets the second state data to show that a constant has not been read from the second constant storage means,
• (d) when the decoding means indicates the second case and the second state data shows that a constant has not been read from the second constant storage means, the constant transfer means transfers the second constant from the instruction register to the second constant storage means without deleting a constant that is stored in the second constant storage means, links the second constant and a valid constant in the second constant storage means, and sets a linking result as a new valid constant;
• and
• execution means for operating as follows
• (i) when the decoding means indicates the third case, the execution means reads the linked constant stored in the first constant storage means and executes the operation using the read constant as an operand,
• (ii) when the decoding means indicates the fourth case, the execution means reads the linked constant stored in the second constant storage means and executes the operation using the read constant as an operand,
• wherein in the third case, after the execution means reads the linked constant stored in the first constant storage means, the constant transfer means sets the first state data to show that the constant has been read from the first constant storage means, and
• in the fourth case, after the execution means reads the linked constant stored in the second constant storage means, the constant transfer means sets the second state data to show that the constant has been read from the second constant storage means.

A processor for executing operations based on instructions, the processor comprising:

• an instruction register for storing an instruction;
• first constant storage means including a first storage region for storing a constant in a first format;
• second constant storage means including a second storage region for storing the constant in a second format;
• decoding means for decoding the instruction stored in the instruction register and indicating one of three cases given below
• (1) a first case where the instruction includes a storage constant that is to be stored in the first constant storage means and the second constant storage means,
• (2) a second case where the constant in the first format is used in an operation, and
• (3) a third case where the constant in the second format is used in an operation;
• constant transfer means for operating as follows
• (a) when the decoding means gives an indication of the first case and no valid constant is stored in the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means, and for setting the transferred storage constant in the first constant storage means and the second constant storage means as valid constants;
• (b) when the decoding means gives an indication of the first case and a valid constant is stored in the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means so that the valid constants are not deleted, links the transferred storage constant with the valid constant in the first constant storage means and the valid constant in the second constant storage means, and sets linking results for the first constant storage means and the second constant storage means as valid constants;
• and
• execution means for reading, when the decoding means gives an indication of the second case, the linked constant stored in the first constant storage means and executing the operation using the read constant, and for reading, when the decoding means gives an indication of the third case, the linked constant stored in the second constant storage means and executing the operation using the read constant.

A processor for executing operations based on instructions, the processor comprising:

• an instruction register for storing an instruction;
• first constant storage means including a first storage region for storing a constant in a first format;
• second constant storage means including a second storage region for storing the constant in a second format;
• decoding means for decoding the instruction stored in the instruction register and indicating one of three cases given below
• (1) a first case where the instruction includes a storage constant that is to be stored in the first constant storage means and the second constant storage means,
• (2) a second case where the constant in the first format is used in an operation, and
• (3) a third case where the constant in the second format is used in an operation;
• constant transfer means for storing state data showing whether a constant has been read from either of the first constant storage means and the second constant storage means, and for operating as follows
• (a) when the decoding means gives an indication of the first case and the state data shows that a constant has been read from one of the first constant storage means and the second constant storage means, the constant transfer means clears the first constant storage means and the second constant storage means, transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means, and changes the state data to show that a constant has not been read from either of the first constant storage means and the second constant storage means, and
• (b) when the decoding means gives an indication of the first case and the state data shows that a constant has not been read from one of the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means so that the respective constants in the first constant storage means and the second constant storage means are not deleted, links the transferred storage constant with the valid constant in the first constant storage means and with the valid constant in the second constant storage means, and sets respective linking results as new constants;
• and
• execution means for reading, when the decoding means gives an indication of the second case, the linked constant stored in the first constant storage means and executing the operation using the read constant, and for reading, when the decoding means gives an indication of the third case, the linked constant stored in the second constant storage means and executing the operation using the read constant,
• wherein in the second case, after the linked constant in the first constant storage means has been read by the execution means, the constant transfer means clears the first storage region and the second storage region, and changes the state data to show that a constant has been read from one of the first constant storage means and the second constant storage means, and
• in the third case, after the linked constant in the first constant storage means has been read by the execution means, the constant transfer means clears the first storage region and the second storage region, and changes the state data to show that a constant has been read from one of the first constant storage means and the second constant storage means.

A VLIW (Very Long Instruction Word) processor for decoding and executing instructions, each instruction including a format field storing a format code showing the instruction format and a plurality of operation fields for indicating operations that are to be executed in parallel, the VLIW processor including:

• an instruction register for storing an instruction;
• first constant storage means including a first storage area;
• second constant storage means including a second storage area;
• decoding means decoding the format field in the instruction stored in the instruction register and, depending on a content of the format field, for giving an indication of one of two cases listed below
• (1) a first case where at least one operation field includes a first constant to be stored into the first constant storage means, and
• (2) a second case where at least one operation field includes a second constant to be stored into the second constant storage means,
• and for decoding the operation field in the instruction stored in the instruction register and, depending on a content of the operation field, for giving an indication of one of two cases listed below
• (3) a third case where a constant stored in the first constant storage means is to be used in at least one operation, and
• (4) a fourth case where a constant stored in the second constant storage means is to be used in at least one operation;
• constant transfer means for operating as follows
• (a) when the decoding means indicates the first case and no valid constant is stored in the first constant storage means, the constant transfer means transfers the first constant from the instruction register to the first constant storage means and sets the transferred first constant in the first constant storage means as a valid constant,
• (b) when the decoding means indicates the first case and a valid constant is stored in the first constant storage means, the constant transfer means transfers the first constant from the instruction register to the first constant storage means so as to retain the valid constant, links the first constant and the valid constant in the first constant storage means, and sets a linking result as a new valid constant,
• (c) when the decoding means indicates the second case and no valid constant is stored in the second constant storage means, the constant transfer means transfers the second constant from the instruction register to the second constant storage means and sets the transferred second constant in the second constant storage means as a valid constant,
• (d) when the decoding means indicates the second case and a valid constant is stored in the second constant storage means, the constant transfer means transfers the second constant from the instruction register to the second constant storage means so as to retain the valid constant, links the second constant and the valid constant in the second constant storage means, and sets a linking result as a new valid constant;
• and
• execution means for operating as follows
• (i) when the decoding means indicates the third case, the execution means reads the linked constant stored in the first constant storage means and executes the operation using the read constant as an operand, and
• (ii) when the decoding means indicates the fourth case, the execution means reads the linked constant stored in the second constant storage means and executes the operation using the read constant as an operand.

A VLIW processor for decoding and executing instructions, each instruction including a format field storing a format code showing the instruction format and a plurality of operation fields for indicating operations that are to be executed in parallel, the VLIW processor including:

• an instruction register for storing an instruction;
• first constant storage means including a first storage area;
• second constant storage means including a second storage area;
• decoding means for decoding the format field in the instruction stored in the instruction register and, depending on a content of the format field, for giving an indication of one of two cases listed below
• (1) a first case where at least one operation field includes a first constant to be stored into the first constant storage means, and
• (2) a second case where at least one operation field includes a second constant to be stored into the second constant storage means,
• and for decoding the operation field in the instruction stored in the instruction register and, depending on a content of the operation field, for giving an indication of one of two cases listed below
• (3) a third case where a constant stored in the first constant storage means is to be used in at least one operation, and
• (4) a fourth case where a constant stored in the second constant storage means is to be used in at least one operation;
• constant transfer means for storing first state data showing whether a constant has been read from the first constant storage means and second state data showing whether a constant has been read from the second constant storage means, and for operating as follows
• (a) when the decoding means indicates the first case and the first state data shows that the constant has been read from the first constant storage means, the constant transfer means clears the first storage region, transfers the first constant from the instruction register to the first constant storage means, and sets the first state data to show that a constant has not been read from the first constant storage means,
• (b) when the decoding means indicates the first case and the first state data shows that a constant has not been read from the first constant storage means, the constant transfer means transfers the first constant from the instruction register to the first constant storage means without deleting a valid constant that is stored in the first constant storage means, links the first constant and the valid constant in the first constant storage means, and sets a linking result as a new valid constant,
• (c) when the decoding means indicates the second case and the second state data shows that the constant has been read from the second constant storage means, the constant transfer means clears the second storage region, transfers the second constant from the instruction register to the second constant storage means, and sets the second state data to show that a constant has not been read from the second constant storage means,
• (d) when the decoding means indicates the second case and the second state data shows that a constant has not been read from the second constant storage means, the constant transfer means transfers the second constant from the instruction register to the second constant storage means without deleting a constant that is stored in the second constant storage means, links the second constant and a valid constant in the second constant storage means, and sets a linking result as a new valid constant;
• and
• execution means for operating as follows
• (i) when the decoding means indicates the third case, the execution means reads the linked constant stored in the first constant storage means and executes the operation using the read constant as an operand, and
• (ii) when the decoding means indicates the fourth case, the execution means reads the linked constant stored in the second constant storage means and executes the operation using the read constant as an operand,
• wherein in the third case, after the execution means reads the linked constant stored in the first constant storage means, the constant transfer means sets the first state data to show that the constant has been read from the first constant storage means, and
• in the fourth case, after the execution means reads the linked constant stored in the second constant storage means, the constant transfer means sets the second state data to show that the constant has been read from the second constant storage means.

A VLIW processor for decoding and executing instructions, each instruction including a format field storing a format code showing the instruction format and a plurality of operation fields for indicating operations that are to be executed in parallel, the VLIW processor including:

• an instruction register for storing an instruction;
• first constant storage means including a first storage region for storing a constant in a first format;
• second constant storage means including a second storage region for storing the constant in a second format;
• decoding means for decoding the format field in the instruction stored in the instruction register and indicating a case given below
• (1) a first case where at least one operation field in the instruction includes a storage constant that is to be stored in the first constant storage means and the second constant storage means,
• and for decoding the operation field in the instruction stored in the instruction register and, depending on a content of the operation field, for giving an indication of one of two cases given below
• (2) a second case where the constant in the first format is used in at least one operation, and
• (3) a third case where the constant in the second format is used in at least one operation;
• constant transfer means for operating as follows—
• (a) when the decoding means gives an indication of the first case and no valid constant is stored in the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means, and for setting the transferred storage constant in the first constant storage means and the second constant storage means as valid constants;
• (b) when the decoding means gives an indication of the first case and a valid constant is stored in the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means so that the valid constants are not deleted, links the transferred storage constant with the valid constant in the first constant storage means and the valid constant in the second constant storage means, and sets linking results for the first constant storage means and the second constant storage means as valid constants,
• the valid constant stored in the first constant storage means being stored in a first format and the valid constant stored in the second constant storage means being stored in a second format;
• and
• execution means for reading, when the decoding means gives an indication of the second case, the linked constant stored in the first constant storage means and executing the operation using the read constant, and for reading, when the decoding means gives an indication of the third case, the linked constant stored in the second constant storage means and executing the operation using the read constant.

A VLIW processor for decoding and executing instructions, each instruction including a format field storing a format code showing the instruction format and a plurality of operation fields for indicating operations that are to be executed in parallel, the VLIW processor including:

• an instruction register for storing an instruction;
• first constant storage means including a first storage region for storing a constant in a first format;
• second constant storage means including a second storage region for storing the constant in a second format;
• decoding means for decoding the format field in the instruction stored in the instruction register and indicating a case given below
• (1) a first case where at least one operation field in the instruction includes a storage constant that is to be stored in the first constant storage means and the second constant storage means,
• and for decoding the operation field in the instruction stored in the instruction register and, depending on a content of the operation field, for giving an indication of one of two cases given below
• (2) a second case where the constant in the first format is used in at least one operation, and
• (3) a third case where the constant in the second format is used in at least one operation;
• constant transfer means for storing state data showing whether a constant has been read from either of the first constant storage means and the second constant storage means, and for operating as follows
• (a) when the decoding means gives an indication of the first case and the state data shows that a constant has been read from one of the first constant storage means and the second constant storage means, the constant transfer means clears the first constant storage means and the second constant storage means, transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means, and changes the state data to show that a constant has not been read from either of the first constant storage means and the second constant storage means,
• (b) when the decoding means gives an indication of the first case and the state data shows that a constant has not been read from one of the first constant storage means and the second constant storage means, the constant transfer means transfers the storage constant from the instruction register to the first constant storage means and the second constant storage means so that the respective constants in the first constant storage means and the second constant storage means are not deleted, links the transferred storage constant with the valid constant in the first constant storage means and with the valid constant in the second constant storage means, and sets respective linking results as new constants;
• and
• execution means for reading, when the decoding means gives an indication of the second case, the linked constant stored in the first constant storage means and executing the operation using the read constant, and for reading, when the decoding means gives an indication of the third case, the linked constant stored in the second constant storage means and executing the operation using the read constant,
• wherein in the second case, after the linked constant in the first constant storage means has been read by the execution means, the constant transfer means clears the first storage region and the second storage region, and changes the state data to show that a constant has been read from one of the first constant storage means and the second constant storage means, and
• in the third case, after the linked constant in the first constant storage means has been read by the execution means, the constant transfer means clears the second storage region and the second storage region, and changes the state data to show that a constant has been read from one of the first constant storage means and the second constant storage means.