US 6,209,078 B1Granted

Accelerated multimedia processor

AssigneeLSI Logic Corporation

InventorsPaul Chiang, Pius Ng, Paul Look

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Abstract

A programmable multimedia accelerator which maximizes data bandwidth utilization with minimal hardware (and consequently minimal power consumption) is provided herein. In one embodiment, the accelerator includes four functional units, a routing unit, and a control module. The functional units each operate on four input bytes and a carry-in bit, and produce two output bytes and a carry-out bit. The carry-out bit of each functional unit is provided as a carry-in bit to another functional unit, allowing the functional units to operate cooperatively to carry out extended-precision operations when needed. The functional units can also operate individually to perform low-precision operations in parallel. The routing unit is coupled to the functional units to receive the output bytes and to provide a permutation of the output bytes as additional pairs of input bytes to the functional units. The control module stores and executes a set of instructions to provide control signals to the functional units and the routing units. The functional units are preferably configured to perform 8×8 bit multiplications and 16 bit operations such as addition, subtraction, logical AND, and logical XOR.

A hardware accelerator which comprises:

an input port;
and
two or more functional units, wherein each functional unit includes:
a first input multiplexer coupled to the input port to receive an first N bit word;
a second input multiplexer coupled to the input port to receive a second N bit word different than the first N bit word;
a third input multiplexer;
a fourth input multiplexer;
an N×N bit multiplier coupled to the first and second input multiplexers to receive the first and second N bit words and configured to multiply the first and second N bit words to produce a most significant N bit word and a least significant N bit word;
a first bypass multiplexer coupled to the multiplier to receive the most significant N bit word and coupled to the first input multiplexer to receive the first N bit word, and further configured to provide a first selected N bit word;
a second bypass multiplexer coupled to the multiplier to receive the least significant N bit word and coupled to the second input multiplexer to receive the second N bit word, and further configured to provide a second selected N bit word;
a 2N bit arithmetic logic unit (ALU) coupled to the first and second bypass multiplexers to receive a first 2N bit operand, and coupled to the third and fourth input multiplexers to receive a second 2N bit operand, wherein the ALU is configured to operate on the first and second 2N bit operands to produce a most significant N bit result word and a least significant N bit result word;
a first register bank coupled to the ALU to receive the most significant N bit result word, and configured to provide a third N bit word to the third input multiplexer and a fourth input word to the fourth multiplexer;
and
a second register bank coupled to the ALU to receive the least significant N bit result word, and configured to provide a fifth N bit word to the third input multiplexer and a sixth N bit word to the fourth input multiplexer.

11 more elements

Abstract

Claims14