Method and apparatus for two-stage address generation

A system for generating an instruction operand address, comprising:

• a first stage means for producing a first-stage sum from zero or more component values, said component values further comprise a segment base, a base, a bit offset, an index, a scale, and a displacement;
• said first stage means further comprises a pre-add logic means for adding zero or more of said component values, a first-stage-bypass means for bypassing zero or more of said component values, wherein said first-stage-bypass means is coupled to said pre-add logic means, and an index scaler means for scaling said index, said index scaler means is coupled to said pre-add logic means and to said first-stage-bypass logic means;
• said index scaler means further comprises an index scale multiplier means for multiplying said index by said scale and providing a scaled index to said pre-add logic means, a scale buffer means for receiving and storing said scale. wherein said scale buffer means is coupled between said multi-cycle bypass signal means and said index scale multiplier means, and an index bypass means for bypassing said index, wherein said index bypass means is coupled between said multi-cycle bypass means and said index scale multiplier means;
• a second stage means for receiving said first-stage sum and for producing the instruction operand address;
• and
• a multi-cycle bypass means for coupling one or more multi-cycle bypass value datapaths to said first stage means and to said second stage means.

A method to manufacture an apparatus that generates an instruction operand address, comprising:

• providing a first stage circuit that produces a first-stage sum from zero or more component values, said component values further comprise a segment base, a base, a bit offset, an index, a scale, and a displacement;
• said step of providing a first stage circuit further comprises providing a pre-add logic circuit, providing a first-stage-bypass logic circuit and coupling said first-stage-bypass logic circuit to said pre-add logic circuit, providing an index scaler circuit, and coupling said index scaler circuit to said pre-add logic circuit and to said first-stage-bypass logic circuit;
• said step of providing an index scaler circuit further comprises providing an index scale multiplier, coupling said index scale multiplier to provide its output to said pre-add logic circuit, providing a scale buffer wherein said scale buffer is coupled to receive said scale as an input, coupling said scale buffer between said multi-cycle bypass value datapath and said index scale multiplier, providing an index bypass mux that is coupled to receive said index as an input, and coupling said index bypass mux between said multi-cycle bypass value datapath and said index scale multiplier;
• providing a second stage circuit that produces the instruction operand address, said second stage circuit is coupled to said first-stage circuit;
• and
• coupling one or more multi-cycle bypass signal datapaths to said first stage circuit and to said second stage circuit.

A method that generates an instruction operand address, comprising:

• generating zero or more multi-cycle bypass values;
• generating a first-stage sum from zero or more component values and zero or more said multi-cycle bypass values, said component values further comprise a segment base, a base, a bit offset, an index, a scale, and a displacement;
• said step of generating a first-stage sum further comprises generating bypass values for zero or more of said component values, scaling said index to produce a scaled index, adding zero or more of said component values and zero or more of said bypass values and said scaled index to produce said first-stage sum;
• said scaling step further comprises providing a bypass value for said index to an index bypass mux, generating an output from said index bypass mux, providing said scale to a scale buffer, passing said scale through said scale buffer, and generating a scaled index by multiplying said scale by the output from said index bypass mux;
• and
• performing second-stage processing to generate the instruction operand address from said base, said first-stage sum, and zero or more said multi-cycle bypass values.