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US 6,209,073 B1Granted
System and method for interlocking barrier operations in load and store queues
AssigneesInternational Business Machines Corporation, Motorola, Inc.
InventorsAlexander Edward Okpisz, Thomas Albert Petersen, Amy May Tuvell, Ronny Lee Arnold
Life of this patent
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Abstract
Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.
Claims21
A processor comprising:
- a load/store unit operable for storing a first storage access instruction and a storage access blocking instruction;
- and
- a pointer scheme operable for ordering the first storage access instruction to access a storage medium before the storage access blocking instruction, and not permitting a second storage access instruction to access the storage medium until after the storage access blocking instruction has completed, wherein accessing of the storage medium by the first and second storage access instructions involves accessing a memory system external to the processor via a bus interface unit, wherein a storage access instruction subsequent to the storage access blocking instruction but able to execute without requiring access to the memory system is not blocked by the storage access blocking instruction.
A processor comprising:
- a load/store unit operable for storing a first storage access instruction and a storage access blocking instruction;
- and
- a pointer scheme operable for ordering the first storage access instruction to access a storage medium before the storage access blocking instruction, and not permitting a second storage access instruction to access the storage medium until after the storage access blocking instruction has completed, wherein the load/store unit includes a load queue and a store queue, wherein the storage access instructions are load and store instructions, wherein the storage access blocking instruction is an EIEIO instruction, wherein the store queue strictly orders the storage access instructions and the EIEIO instruction relative to each other, and wherein the pointer scheme:
- (1) requires any store instruction ordered before the EIEIO instruction to access the storage medium before completion of the EIEIO instruction;
- (2) requires any load instruction pointing to the EIEIO instruction to access the storage medium before completion of the EIEIO instruction;
- and (3) does not permit a subsequently ordered load instruction not pointing to the EIEIO instruction to access the storage medium before completion of the EIEIO instruction.
3 more elements
A processor comprising:
- a load/store unit operable for storing a first storage access instruction and a storage access blocking instruction;
- and
- a pointer scheme operable for ordering the first storage access instruction to access a storage medium before the storage access blocking instruction, and not permitting a second storage access instruction to access the storage medium until after the storage access blocking instruction has completed, wherein the load/store unit includes a load queue and a store queue, wherein the storage access instructions are load and store instructions, wherein the storage access blocking instruction is an EIEIO instruction, wherein the load queue strictly orders the storage access instructions and the EIEIO instruction relative to each other, and wherein the pointer scheme:
- (1) requires any load instruction ordered before the EIEIO instruction to access the storage medium before completion of the EIEIO instruction;
- (2) requires any store instruction pointing to the EIEIO instruction to access the storage medium before completion of the EIEIO instruction;
- and (3) does not permit a subsequently ordered store instruction not pointing to the EIEIO instruction to access the storage medium before completion of the EIEIO instruction.
3 more elements
A method for executing storage access instructions in a processor, comprising the steps of:
- queuing a first load instruction into a load queue in a load/store unit;
- queuing a first storage access blocking instruction in a store queue in the load/store unit;
- queuing a second load instruction into the load queue;
- and
- inhibiting the access of a storage medium by the second load instruction until after completion of the first storage access blocking instruction.
2 more elements
A method for executing storage access instructions in a processor, comprising the steps of:
- queuing a first store instruction into a store queue in a load/store unit;
- queuing a first storage access blocking instruction in a load queue in the load/store unit;
- queuing a second store instruction into the store queue;
- and
- inhibiting the access of a storage medium by the second store instruction until after completion of the first storage access blocking instruction.
2 more elements
A processor comprising:
- a load/store unit including a load queue and a store queue;
- a cache coupled to the load/store unit;
- a bus interface unit coupled to the load/store unit and adaptable for coupling to a system memory via a bus;
- circuitry operable for storing a first load instruction in the load queue, wherein the first load instruction is operable for reading data from the system memory;
- circuitry operable for storing an EIEIO-type instruction in the store queue;
- circuitry operable for storing a second load instruction in the load queue, wherein the second load instruction is operable for reading data from the system memory;
- and
- circuitry operable for inhibiting access of the bus by the second load instruction until after the EIEIO-type instruction has completed.
5 more elements
Dependencies are inferred from the claim text.