Source synchronous interface between master and slave using a deskew latch

A method comprising:

• issuing a request from a processor to a cache memory;
• executing the request in the cache memory asynchronously with respect to clock cycles in the processor;
• retrieving data requested by a command;
• generating timing information;
• sending the data and the timing information from the cache memory to the processor;
• and
• latching, in a deskew latch, the data in response to the timing information.

An integrated circuit (IC) package, comprising;

• a cache memory subsystem;
• a processor having a plurality of deskew latches;
• and
• a bus coupled between the cache memory subsystem and the processor, wherein the bus communicates a command from the processor to the cache memory subsystem and the bus further communicates timing information and data accessed in response to the command from the cache memory subsystem to the processor and a bus interface is configured to provide access by the processor to one or more peripheral device;
• wherein the cache memory subsystem operates asynchronously with respect to a system clock in response to the command to output the data and the timing information, and further wherein the data is latched in the deskew latches in response to the timing information.

An apparatus comprising:

• means for issuing a request from a processor to a cache memory;
• means for executing the request in the cache memory asynchronously with respect to clock cycles in the processor;
• means for retrieving data requested by a command;
• means for generating timing information;
• means for sending the data and the timing information from the cache memory to the processor;
• and
• means for latching the data in response to the timing information.