Asynchronous request/synchronous data dynamic random access memory

A memory system comprising:

• a memory device having a plurality of modes including a first mode and a second mode;
• the memory device assuming a lower power state in which data transfer circuits within said memory device are not driven by an internal clock signal when said memory device is in said first mode;
• the memory device assuming a higher power state in which said data transfer circuits are driven by said internal clock signal when said memory device is in said second mode;
• a memory controller coupled to said memory device by a plurality of lines;
• the memory controller asynchronously sending a first set of control signals that specify a data transfer transaction to said memory device;
• the memory controller asynchronously transmitting a clock control signal to said memory device such that said memory device to assumes said second mode;
• and
• the memory device assuming said second mode in response to said clock control signal and driving said data transfer circuits with said internal clock signal to perform the data transfer transaction specified by said first set of control signals.

A method for performing a data transfer in a computer system, the method comprising:

• a memory device having data transfer circuitry said memory device assuming a first mode in which said data transfer circuitry is not driven by any clock signal;
• asynchronously sending control information and address information to said memory device, said control information specifying a data transfer transaction, said address information specifying storage within said memory device that will be involved in said data transfer transaction;
• in response to said control information, said memory device assuming a second mode in which said data transfer circuitry is driven by a clock signal;
• and
• said memory device performing said data transfer transaction in synchronism with said clock signal while said memory device is in said second mode.