Read line buffer and signaling protocol for processor
AssigneeIntel Corporation
InventorsDavid L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch
Life of this patent
Estimating the term…
Abstract
A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
Claims12
A method of controlling a read transaction for a processor, comprising:
- generating a request on an external bus for data to be read to the processor,
- reading the requested data from the external bus to an intermediate memory in the processor,
- reading the requested data from the intermediate memory to a destination,
- when the intermediate memory is full, generating a stalling signal on the external bus until the intermediate memory is no longer full.
A bus sequencing unit for a processor, comprising
- a bus sequencing queue having a queue memory with a plurality of entries,
- an external bus controller, coupled to the bus sequencing queue and to an external bus,
- a read line buffer coupled to the external bus and having a buffer memory with a plurality of entries, the number of read line buffer entries being less than the number of queue memory entries, an identifier memory providing a plurality of entries, one associated with each entry of the queue memory, wherein requests to be executed on the external bus are stored in the queue memory and an identification of a read line buffer entry associated with the request is stored an associated entry in the identifier memory.
A method of processing bus transactions generated by a processor, comprising:
- receiving a request for a bus transaction,
- queuing the request in a memory,
- issuing the request on an external bus,
- pursuant to the request, reading the data into the processor,
- before data to be read to the processor is present on the external bus, determining whether the processor may receive the data,
- when the processor cannot receive the data, generating a stalling signal on the external bus until the processor may receive the data.
A method of controlling a read transaction for a processor, comprising:
- posting a request on an external bus for data to be read to the processor;
- when an intermediate memory is full and prior to a time that data is to be read to the processor pursuant to the request, generating a stall signal on an external bus until the intermediate memory is no longer full;
- and
- thereafter:
- reading the requested data from the external bus to the intermediate memory in the processor, and
- reading the requested data from the intermediate memory to a destination.
Dependencies are inferred from the claim text.