A method for improving memory performance in a processor, said processor including at least main memory, a cache memory and an overlay memory, said overlay memory providing said processor with high speed access to data stored therein, said method comprising the steps of:
- a) allocating to said overlay memory a span of addresses within said main memory, and maintaining unchanged allocation of said span of addresses to said overlay memory during execution of a program;
- b) responding to access by a program of data from said span of addresses by (i) enabling said overlay memory to respond to said access, and (ii) invariably inhibiting transmission of an address in said span of addresses to said main memory during an entire time of said execution of said program when said span of addresses is assigned to said overlay memory, wherein data written to said overlay memory is not written to said cache memory.