Reliable interrupt reception over buffered bus
AssigneeCisco Technology, Inc.
InventorGlenn E. Lee
Life of this patent
Estimating the term…
Abstract
A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.
Claims18
A method for writing data from an initiating device to target device over a buffered bus, comprising:
- dividing the data into a plurality of data blocks;
- sending all but the last data block over the buffered bus using a posted write transaction;
- and
- sending the last data block over the buffered bus using a delayed write transaction.
A method for writing data from an initiating device to a target device in communication with a processor, said data written over a buffered bus, said method comprising:
- sending the data over the buffered bus using a posted write transaction;
- and
- sending an interrupt request to the processor over the buffered bus using a delayed write transaction after completing the sending of the data.
An apparatus for writing data from an initiating device to a target device, comprising:
- a data divider associated with the initiating device, said data divider dividing the data into a plurality of data blocks;
- a buffered bus in communication with the data divider and the target device;
- and
- a bridge disposed in the buffered bus, said bridge supporting delayed write and posted write transactions for transmitting data from an initiating side to a target side of said bridge.
An apparatus for writing data from an initiating device to target device, comprising:
- a buffered bus in communication with the initiating device, said buffered bus receiving a multi-data-block communication from the initiating device;
- and;
- a bridge disposed in the buffered bus, said bridge supporting delayed write and posted write transactions.
Dependencies are inferred from the claim text.