DMA transfer from a storage unit to a host using at least two transfer rates and cyclic error detection

A data transfer unit for transferring data using direct memory access (DMA) between a storage unit and a host, comprising:

• data transfer means for transferring data using DMA at one of at least first and second data transfer rates where the second data transfer rate is slower than the first data transfer rate;
• error detection means for detecting a predetermined type of error in transferring the data;
• control means for transferring data between the storage unit and the host at the first data transfer rate until an error of the predetermined type of error is detected by the error detection means whereupon the data is temporarily transferred at the second data transfer rate until a specified event occurs;
• calculation means for calculating cyclicity of a plurality of error occurrences of the predetermined error type at the second data transfer rate;
• and
• control means for inserting a predetermined wait to avoid transferring data at the cyclicity of the plurality of error occurrences of the predetermined error type.