Computer system having two DMA circuits assigned to the same address space

An information processing system, comprising:

• a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;
• a bus defining an interconnection between said CPU and peripheral devices across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal;
• a first DMA controller, connected to said bus, to which a predetermined I/O address is assigned;
• a second DMA controller, connected to said bus, to which said predetermined I/O address is assigned;
• a first connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first DMA controller;
• a second connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said second DMA controller;
• and
• controller logic, connected to said bus, which receives said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second DMA controllers, and directs opening and closing of said first and said second connection/disconnection switches in accordance with I/O accesses that occur on said bus wherein, when a request for access to said predetermined I/O address occurs, said controller logic disconnects said first and said second connection/disconnection switches, and activates (1) said device select (DEVSEL) signal and (2) said target ready (TRDY) signal on said bus in response to said target ready (TRDY) signal being output by both of said first and said second DMA controllers.

An information processing system, comprising:

• a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;
• a bus defining an interconnection between said CPU and peripheral devices across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal;
• a first DMA controller, connected to said bus, to which a predetermined I/O address is assigned;
• a second DMA controller, connected to said bus, to which said predetermined I/O address is assigned;
• a first connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first DMA controller;
• a second connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said second DMA controller;
• and
• controller logic, connected to said bus, which receives said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second DMA controllers, and directs opening and closing of said first and said second connection/disconnection switches in accordance with I/O accesses that occur on said bus wherein, when a request for access to said predetermined I/O address occurs, said controller logic does not terminate an access cycle, by inhibiting the activation of said target ready (TRDY) signal on said bus, until said target ready (TRDY) signal is output by both of said first and said second DMA controllers.

An information processing system, comprising:

• a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;
• said CPU communicating with peripheral devices via a bus across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal;
• a first peripheral device, connected to said bus, for which a predetermined I/O address is assigned;
• a second peripheral device, connected to said bus, for which said predetermined I/O address is assigned;
• a first connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first peripheral device;
• a second connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output by said second peripheral device;
• and
• controller logic, connected to said bus, for receiving said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second peripheral devices, and for opening and closing said first and said second connection/disconnection switches in response to I/O accesses that occur on said bus, wherein said controller logic disconnects said first and said second connection/disconnection switches during a bus cycle wherein said predetermined I/O address is accessed.

An information processing system, comprising:

• a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;
• said CPU communicating with peripheral devices via a bus across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal;
• a first peripheral device, connected to said bus, for which a predetermined I/O address is assigned;
• a second peripheral device, connected to said bus, for which said predetermined I/O address is assigned;
• a first connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first peripheral device;
• a second connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output by said second peripheral device;
• and
• controller logic, connected to said bus, for receiving said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second peripheral devices, and for opening and closing said first and said second connection/disconnection switches in response to I/O accesses that occur on said bus wherein, when a request occurs for access to said predetermined I/O address, said controller logic disconnects said first and said second connection/disconnection switches, and activates said device select (DEVSEL) signal on said bus and said target ready (TRDY) signal on said bus in response to said target ready (TRDY) signal being output by both of said first and said second peripheral devices.

An information processing system, comprising:

• a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;
• said CPU communicating with peripheral devices via a bus across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal;
• a first peripheral device, connected to said bus, for which a predetermined I/O address is assigned;
• a second peripheral device, connected to said bus, for which said predetermined I/O address is assigned;
• a first connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first peripheral device;
• a second connection/disconnection switch for connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output by said second peripheral device;
• and
• controller logic, connected to said bus, for receiving said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second peripheral devices, and for opening and closing said first and said second connection/disconnection switches in response to I/O accesses that occur on said bus wherein, when a request occurs for access to said predetermined I/O address, said controller logic does not terminate the access cycle, by inhibiting the activation of said target ready (TRDY) signal on said bus, until said target ready (TRDY) signal is output by both of said first and said second peripheral devices.